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PrimeSoc Technologies Interview Questions and Answers
PrimeSoc Technologies Interview Experiences
5 interviews found
Anonymous
Selected
I appeared for an interview before Mar 2024.
(2 Questions)
- Q1. Can you introduce yourself?
- Q2. What are your strengths and weaknesses?
(1 Question)
- Q1. What is your understanding of our company?
Manager - HR & Administration Interview Questions asked at other Companies
Verbal communication and logical aptitude questions test
(2 Questions)
- Q1. What is Universal Asynchronous Receiver Transmitter?
- Ans.
Universal Asynchronous Receiver Transmitter is a hardware device used for serial communication.
UART is commonly used for asynchronous communication between devices
It consists of a transmitter and a receiver
Data is sent in a serial format with start and stop bits
Common baud rates include 9600, 19200, 38400, etc.
- Q2. What is Arm advanced microcontroller based bus architecture?
- Ans.
Arm advanced microcontroller based bus architecture is a high-performance, low-power bus architecture designed for Arm microcontrollers.
Designed for Arm microcontrollers to provide high performance and low power consumption
Supports advanced features like multiple bus masters, bus arbitration, and bus error handling
Commonly used in embedded systems and IoT devices
Examples include Arm Cortex-M series microcontrollers wit
Interview Preparation Tips
Skills evaluated in this interview
Design & Verification Engineer Interview Questions asked at other Companies
VIJAYALAXMANASEN A
Selected
I applied via Campus Placement and was interviewed in Jul 2024. There were 3 interview rounds.
Medium Level Aptitute
Coding Test from Verilog
(2 Questions)
- Q1. Self Introduction
- Q2. Are you okay with 3 years Bond aggrement
- Ans.
Yes, I am okay with a 3-year bond agreement for FPGA Validation.
I am willing to commit to a 3-year bond agreement for the opportunity in FPGA Validation.
I understand the importance of stability and commitment in the field of FPGA Validation.
I am confident in my skills and abilities to contribute effectively during the bond period.
Interview Preparation Tips
Selected
I applied via LinkedIn and was interviewed in Apr 2024. There was 1 interview round.
(2 Questions)
- Q1. How to driver is communicating with sequencer?
- Ans.
The driver communicates with the sequencer through signals and interfaces.
Driver sends commands and data to the sequencer through communication interfaces like SPI, I2C, or UART.
Sequencer receives the commands and data, processes them, and generates appropriate responses.
Communication between driver and sequencer can also involve handshaking signals to ensure data integrity and synchronization.
- Q2. Cretae mHZ clock
Design & Verification Engineer Interview Questions asked at other Companies
PrimeSoc Technologies interview questions for popular designations
Selected
Simple aptitude. Average and quantitative
(1 Question)
- Q1. Ask to write code
Interview Preparation Tips
Test Engineer Interview Questions asked at other Companies
Interview questions from similar companies
anurag kvs
I applied via Job Portal
(1 Question)
- Q1. 1) Explain flipflops 2) UVM Architecture 3)constraints
- Ans.
Flip-flops are sequential logic circuits used to store and manipulate binary data.
Flip-flops are basic building blocks of digital circuits.
They can store a single bit of information, either 0 or 1.
Flip-flops have two stable states: set and reset.
They are used to store and transfer data in sequential circuits.
Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.
Selected
I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.
All aptitude topics covered
(2 Questions)
- Q1. And gate code in behavioral
- Ans.
Implementing an AND gate in behavioral code
Use if statements to check if both inputs are high
Assign the output to high if both inputs are high
Use Verilog or VHDL syntax depending on the language being used
- Q2. Difference between Ff & latch
- Ans.
FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.
FF stores data on clock edge, latch stores data as long as enable signal is active
FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)
FF is used for sequential circuits, latch is used for level-sensitive circuits
Example: D flip-flop (FF) vs SR latch
Interview Preparation Tips
- Design
I applied via Campus Placement and was interviewed before Jul 2021. There were 4 interview rounds.
Aptitude test on CS subjects like C programming, DBMS, CN, and OS.
There were 2 input-output based questions of easy to moderate level
Every candidate was given an individual topic and was asked to speak on it
(1 Question)
- Q1. Some typical HR questions
Interview Preparation Tips
I applied via Company Website and was interviewed before Dec 2020. There were 4 interview rounds.
Interview Questionnaire
1 Question
- Q1. Questions on Java,SQL,some trending technologies(IOT,Big data),pattern questions, programming questions with different approaches.
Interview Preparation Tips
I applied via Referral and was interviewed before Jan 2021. There was 1 interview round.
Interview Questionnaire
1 Question
- Q1. Java questions
Interview Preparation Tips
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Rating in categories
|
Verification Engineer
4
salaries
|  ₹2.7 L/yr - ₹4.7 L/yr |
|
Design & Verification Engineer
3
salaries
| ₹2.5 L/yr - ₹3 L/yr |
|
Fpga Design Engineer
3
salaries
| ₹1.2 L/yr - ₹3 L/yr |
|
Vlsi Verification Engineer
3
salaries
| ₹1.2 L/yr - ₹3 L/yr |
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