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PrimeSoc Technologies Design & Verification Engineer Interview Questions and Answers

Updated 28 Oct 2024

PrimeSoc Technologies Design & Verification Engineer Interview Experiences

2 interviews found

Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Verbal communication and logical aptitude questions test

Round 2 - Technical 

(2 Questions)

  • Q1. What is Universal Asynchronous Receiver Transmitter?
  • Ans. 

    Universal Asynchronous Receiver Transmitter is a hardware device used for serial communication.

    • UART is commonly used for asynchronous communication between devices

    • It consists of a transmitter and a receiver

    • Data is sent in a serial format with start and stop bits

    • Common baud rates include 9600, 19200, 38400, etc.

  • Answered by AI
  • Q2. What is Arm advanced microcontroller based bus architecture?
  • Ans. 

    Arm advanced microcontroller based bus architecture is a high-performance, low-power bus architecture designed for Arm microcontrollers.

    • Designed for Arm microcontrollers to provide high performance and low power consumption

    • Supports advanced features like multiple bus masters, bus arbitration, and bus error handling

    • Commonly used in embedded systems and IoT devices

    • Examples include Arm Cortex-M series microcontrollers wit

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - This is was very worst experience and they won't respect the candidate and the employee. I wish not to go, to join the company.

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via LinkedIn and was interviewed in Apr 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to driver is communicating with sequencer?
  • Ans. 

    The driver communicates with the sequencer through signals and interfaces.

    • Driver sends commands and data to the sequencer through communication interfaces like SPI, I2C, or UART.

    • Sequencer receives the commands and data, processes them, and generates appropriate responses.

    • Communication between driver and sequencer can also involve handshaking signals to ensure data integrity and synchronization.

  • Answered by AI
  • Q2. Cretae mHZ clock

Design & Verification Engineer Interview Questions Asked at Other Companies

asked in Frenus Tech
Q1. 1. XOR gate 2. How you compare two 4 bit numbers only using gates ... read more
Q2. Why $cast is used? Types of arrays
Q3. Explain setup time and hold time and what is the importance of se ... read more
Q4. What is mux? What are the use of select lines in mux?
asked in Samsung
Q5. how to call an interface signal at sequence level in uvm?

Interview questions from similar companies

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-

I applied via Job Portal

Round 1 - One-on-one 

(1 Question)

  • Q1. 1) Explain flipflops 2) UVM Architecture 3)constraints
  • Ans. 

    Flip-flops are sequential logic circuits used to store and manipulate binary data.

    • Flip-flops are basic building blocks of digital circuits.

    • They can store a single bit of information, either 0 or 1.

    • Flip-flops have two stable states: set and reset.

    • They are used to store and transfer data in sequential circuits.

    • Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.

  • Answered by AI
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

All aptitude topics covered

Round 2 - Technical 

(2 Questions)

  • Q1. And gate code in behavioral
  • Ans. 

    Implementing an AND gate in behavioral code

    • Use if statements to check if both inputs are high

    • Assign the output to high if both inputs are high

    • Use Verilog or VHDL syntax depending on the language being used

  • Answered by AI
  • Q2. Difference between Ff & latch
  • Ans. 

    FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.

    • FF stores data on clock edge, latch stores data as long as enable signal is active

    • FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)

    • FF is used for sequential circuits, latch is used for level-sensitive circuits

    • Example: D flip-flop (FF) vs SR latch

  • Answered by AI

Interview Preparation Tips

Topics to prepare for Wipro Design & Verification Engineer interview:
  • Design
Interview preparation tips for other job seekers - all basics covered

I applied via Walk-in and was interviewed before Dec 2020. There were 3 interview rounds.

Interview Questionnaire 

3 Questions

  • Q1. Basic Programming questions.
  • Q2. Fibonacci program
  • Q3. OOPS concepts.

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basic OOPS concepts and basic programs.

I applied via Naukri.com and was interviewed in Aug 2020. There were 3 interview rounds.

Interview Questionnaire 

1 Question

  • Q1. Oops Concepts and Data Structure Questions.

Interview Preparation Tips

Interview preparation tips for other job seekers - Oops And Data Structure, Collection.

I applied via Recruitment Consultant and was interviewed in Nov 2020. There were 3 interview rounds.

Interview Questionnaire 

1 Question

  • Q1. Basic communication skills were tested. Sone techical questn too. Versant test is mandatory

Interview Preparation Tips

Interview preparation tips for other job seekers - Please never go for these third party vendors. They misguide you regarding profile . I went for this third party vendor named savantis solution and it really misguided me

I applied via Campus Placement and was interviewed before Feb 2020. There were 6 interview rounds.

Interview Questionnaire 

4 Questions

  • Q1. Was interviewed as fresher?
  • Q2. Written test conducted? with verbal ability test ? GD
  • Q3. How would u deal with a problematic situation when you are working in a team?
  • Q4. What are your plans about higher studies?

Interview Preparation Tips

Interview preparation tips for other job seekers - it was basic with apptiude test and attitiude test.

Interview Questionnaire 

2 Questions

  • Q1. They asked me on java and I have joined as a fresher they not much questions as I got selected as fresher on oops concepts and collections
  • Q2. Please be confident while facing interview and they will check your communication skills

Interview Questionnaire 

1 Question

  • Q1. Who is the most important person have to transform you in your life?

Interview Preparation Tips

Interview preparation tips for other job seekers - Just speak your mind you will be selected.

PrimeSoc Technologies Interview FAQs

How many rounds are there in PrimeSoc Technologies Design & Verification Engineer interview?
PrimeSoc Technologies interview process usually has 1-2 rounds. The most common rounds in the PrimeSoc Technologies interview process are Technical and Aptitude Test.
What are the top questions asked in PrimeSoc Technologies Design & Verification Engineer interview?

Some of the top questions asked at the PrimeSoc Technologies Design & Verification Engineer interview -

  1. What is Universal Asynchronous Receiver Transmitt...read more
  2. What is Arm advanced microcontroller based bus architectu...read more
  3. how to driver is communicating with sequenc...read more

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PrimeSoc Technologies Design & Verification Engineer Interview Process

based on 2 interviews

Interview experience

3
  
Average
View more

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PrimeSoc Technologies Design & Verification Engineer Reviews and Ratings

based on 2 reviews

1.0/5

Rating in categories

2.7

Skill development

1.0

Work-life balance

1.0

Salary

1.0

Job security

1.0

Company culture

1.0

Promotions

1.0

Work satisfaction

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