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Verbal communication and logical aptitude questions test
Universal Asynchronous Receiver Transmitter is a hardware device used for serial communication.
UART is commonly used for asynchronous communication between devices
It consists of a transmitter and a receiver
Data is sent in a serial format with start and stop bits
Common baud rates include 9600, 19200, 38400, etc.
Arm advanced microcontroller based bus architecture is a high-performance, low-power bus architecture designed for Arm microcontrollers.
Designed for Arm microcontrollers to provide high performance and low power consumption
Supports advanced features like multiple bus masters, bus arbitration, and bus error handling
Commonly used in embedded systems and IoT devices
Examples include Arm Cortex-M series microcontrollers wit
I applied via LinkedIn and was interviewed in Apr 2024. There was 1 interview round.
The driver communicates with the sequencer through signals and interfaces.
Driver sends commands and data to the sequencer through communication interfaces like SPI, I2C, or UART.
Sequencer receives the commands and data, processes them, and generates appropriate responses.
Communication between driver and sequencer can also involve handshaking signals to ensure data integrity and synchronization.
I applied via Job Portal
Flip-flops are sequential logic circuits used to store and manipulate binary data.
Flip-flops are basic building blocks of digital circuits.
They can store a single bit of information, either 0 or 1.
Flip-flops have two stable states: set and reset.
They are used to store and transfer data in sequential circuits.
Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.
I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.
All aptitude topics covered
Implementing an AND gate in behavioral code
Use if statements to check if both inputs are high
Assign the output to high if both inputs are high
Use Verilog or VHDL syntax depending on the language being used
FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.
FF stores data on clock edge, latch stores data as long as enable signal is active
FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)
FF is used for sequential circuits, latch is used for level-sensitive circuits
Example: D flip-flop (FF) vs SR latch
I applied via Walk-in and was interviewed before Dec 2020. There were 3 interview rounds.
I applied via Naukri.com and was interviewed in Aug 2020. There were 3 interview rounds.
I applied via Recruitment Consultant and was interviewed in Nov 2020. There were 3 interview rounds.
I applied via Campus Placement and was interviewed before Feb 2020. There were 6 interview rounds.
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