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I applied via Campus Placement and was interviewed in Sep 2023. There were 2 interview rounds.
Ist round u have to attempt a OA which includes aptitude , logical reasoning and ece related circuit diagram outputs (analog and digital circuit designs)
I applied via Campus Placement and was interviewed in Nov 2023. There was 1 interview round.
I applied via Recruitment Consulltant and was interviewed before Nov 2023. There was 1 interview round.
CGC cell is a standard cell used in physical design with specific characteristics for circuit implementation.
CGC cell stands for Custom Gate Cell, which is a standard cell used in physical design for implementing logic functions.
CGC cells have specific characteristics like fixed height and width, predefined power and ground connections, and a set of pins for input and output signals.
When designing a circuit using CGC c...
Tie cell diagram for low/high cells in physical design engineering.
Tie cell diagram is used in physical design to connect multiple power domains.
Low tie cells are used to connect low power domains, while high tie cells are used for high power domains.
Examples of tie cells include power switches and isolation cells.
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Nvidia interview questions for popular designations
Artificial intelligence is the simulation of human intelligence processes by machines, especially computer systems.
AI involves machines learning from data, recognizing patterns, and making decisions.
Examples of AI include virtual assistants like Siri, self-driving cars, and recommendation systems.
AI can be categorized into narrow AI (specific tasks) and general AI (human-like intelligence).
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I applied via Naukri.com and was interviewed in Sep 2023. There were 3 interview rounds.
I applied via Campus Placement and was interviewed in Sep 2023. There were 2 interview rounds.
2 Coding Questions and approx 20 MCQs where there in the Online Assisment
2 Easy leetcode ques
mcqs on cs funcamentals
I applied via Campus Placement and was interviewed in Aug 2023. There was 1 interview round.
A D flip flop is a sequential logic circuit that stores a single bit of data.
A D flip flop has a data input (D), a clock input (CLK), and an output (Q).
The output (Q) of a D flip flop changes only when the clock input (CLK) transitions from low to high.
The output (Q) of a D flip flop follows the value of the data input (D) when the clock input (CLK) transitions from low to high.
The Verilog code for a D flip flop can be
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