Filter interviews by
Clear (1)
Digital design problems involve challenges in designing and implementing digital circuits and systems.
Understanding and optimizing power consumption
Ensuring signal integrity and minimizing noise
Implementing efficient clocking strategies
Addressing timing issues and meeting performance requirements
There are 3 patterns to detect faults on an XOR gate.
There are 3 possible fault patterns on an XOR gate: Stuck-At-0, Stuck-At-1, and Inversion.
Stuck-At-0 fault pattern occurs when one input is always 0, regardless of the other input.
Stuck-At-1 fault pattern occurs when one input is always 1, regardless of the other input.
Inversion fault pattern occurs when the output is inverted compared to the correct XOR gate output.
Top trending discussions
I applied via Referral and was interviewed in Jun 2022. There was 1 interview round.
Compression ratio can be tweaked by adjusting the volume of the combustion chamber. This affects fuel efficiency and power output.
Compression ratio is the ratio of the volume of the combustion chamber at its largest to its smallest.
Increasing compression ratio can improve fuel efficiency and power output, but too high a ratio can cause engine knocking.
Factors that impact compression ratio include the size and shape of ...
I have observed hold and setup violations in my design and took necessary actions.
I used static timing analysis (STA) to identify hold and setup violations.
I fixed hold violations by adding delay cells or increasing clock period.
I fixed setup violations by reducing delay or decreasing clock period.
I also checked for false paths and multi-cycle paths.
I re-ran STA after fixing violations to ensure timing closure.
I docume...
Explanation of purpose of occ controllers, scan enable signals, lock up latch and arrangement of negative and positive edge triggered flops.
The purpose of occ controllers is to manage the clock signals in a design and ensure proper timing.
Scan enable signals are used for testing and debugging purposes.
Pipelined signals are used for faster data transfer while non-pipelined signals are used for simpler designs.
Lock up la...
Resetting a tap controller without trst signals and finding coverage gaps.
For resetting a tap controller without trst signals, we can use a power-on reset circuit or a watchdog timer.
To find coverage gaps, we can use code coverage analysis tools like CodeSonar, Coverity, or LDRA.
We can also use dynamic analysis tools like Valgrind or Purify to find runtime errors and coverage gaps.
Manual testing and peer code reviews c...
posted on 13 Sep 2024
No violations faced
No, I have not faced any violations in my career
I always make sure to adhere to all rules and regulations in my work
I prioritize ethical conduct and compliance with industry standards
I applied via Referral and was interviewed in Mar 2024. There were 2 interview rounds.
They asked about whallenges i faced inpast
DFt task abd past experience
posted on 29 Oct 2024
I was interviewed before Feb 2023.
Practice on hackerrank, they send hackerrank link for screening round.
I applied via Referral and was interviewed in Sep 2023. There were 4 interview rounds.
The length of the longest common subsequence in given strings is found using dynamic programming.
Use dynamic programming to find the length of the longest common subsequence.
Compare characters of the strings and build a matrix to store the lengths of common subsequences.
Traverse the matrix to find the length of the longest common subsequence.
Write the algorithm for topological sorting.
CAP theorem states that in a distributed system, it is impossible to simultaneously guarantee consistency, availability, and partition tolerance.
Consistency: All nodes in the system have the same data at the same time.
Availability: Every request gets a response, even if some nodes are down.
Partition Tolerance: The system continues to operate despite network partitions.
In a distributed system, you can only achieve two o...
I applied via Company Website and was interviewed before Oct 2022. There were 2 interview rounds.
I applied via Qualcomm Careers and was interviewed in Dec 2023. There were 4 interview rounds.
based on 3 interviews
Interview experience
Processing Executive
1.1k
salaries
| ₹0 L/yr - ₹0 L/yr |
Quality Analyst
144
salaries
| ₹0 L/yr - ₹0 L/yr |
Software Engineer
141
salaries
| ₹0 L/yr - ₹0 L/yr |
Data Analyst
119
salaries
| ₹0 L/yr - ₹0 L/yr |
Senior Software Engineer
104
salaries
| ₹0 L/yr - ₹0 L/yr |
Qualcomm
Intel
Advanced Micro Devices
Micron Technology