DFT Engineer Interview Questions and Answers

Coverage loss can occur due to test pattern compression, test pattern generation, and test application issues.

• Test pattern compression can cause loss of coverage due to the reduction in the number of test patterns.

• Test pattern generation can result in coverage loss if the generated patterns do not cover all the faults.

• Test application issues such as timing violations or signal integrity problems can also lead to coverage loss.

• Coverage loss can also occur due to design changes...read more

Yes, hold time/setup violation can occur at stuckat capture.

• Stuck-at faults can cause hold time violations if the data is not held long enough for the capture register to sample it.

• Similarly, setup violations can occur if the data is not stable before the capture register samples it.

• These violations can be avoided by proper timing constraints and clocking strategies.

• For example, adding a delay to the clock signal can ensure that the data is stable before the capture register ...read more

T3 and T5 violations are related to timing constraints in digital circuits.

• T3 violation occurs when the data arrives too late at the destination register.

• T5 violation occurs when the data arrives too early at the destination register.

• T3 and T5 violations can cause setup and hold time violations.

• T3 and T5 violations can be fixed by adjusting the timing constraints or by adding delay elements.

• Examples of T3 and T5 violations can be found in high-speed digital designs such as mi...read more

Issues faced in post silicon for DFT Engineer

• Coverage gaps can occur due to incomplete testing of certain functionalities

• Wrapper cell issues can arise due to incorrect placement or sizing of the cells

• Post silicon issues can also include timing violations, power issues, and signal integrity problems

• Debugging post silicon issues can be challenging and time-consuming