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Ignitarium Technology Solutions
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I applied via LinkedIn and was interviewed in Dec 2024. There was 1 interview round.
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I applied via Referral and was interviewed before Jun 2021. There were 2 interview rounds.
They asked are u able to work for 12-13 hours and give 3 to 4 simple maths questions in written to solve . They asked for having any health issues because if u r not physically fit then not able to work for 12 to 13 hours a day. A perfect professional company just for earning profit nothing is good for the engineer or workers .
A one line for Apar industry - "Naam bade aur darshan chhote ". Only the hard one survive there if 20 persons start the job , after a year only 2 or 3 person able to survive there .
I am interested in Freescale because of their innovative technology and strong reputation in the industry.
Freescale has a history of developing cutting-edge technology
Their reputation in the industry is strong and respected
I am excited about the opportunity to work with a company that values innovation and excellence
posted on 28 Aug 2016
I applied via Campus Placement
I applied via Campus Placement and was interviewed before Jan 2021. There were 3 interview rounds.
A cache is a high-speed data storage layer that stores frequently accessed data to reduce access time. A tag is used to identify the location of data in the cache.
Cache is a temporary storage that holds frequently accessed data
It reduces the access time by providing faster access to data
Tag is used to identify the location of data in the cache
Tag is a part of the cache memory address
Cache can be implemented in hardware...
C Coding questions
IV characteristics of CMOS inverter show the relationship between input voltage and output current.
CMOS inverter has two transistors - NMOS and PMOS connected in series.
For low input voltage, NMOS is ON and PMOS is OFF, resulting in low output voltage.
For high input voltage, NMOS is OFF and PMOS is ON, resulting in high output voltage.
The transition between low and high output voltage occurs at the threshold voltage.
Th...
Set up time and hold time are timing requirements in digital circuits to ensure proper operation.
Set up time is the minimum time before the clock edge that the input signal must be stable.
Hold time is the minimum time after the clock edge that the input signal must be maintained stable.
Violating set up time can lead to incorrect data being latched.
Violating hold time can lead to metastability issues.
Examples: In a flip...
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Senior Engineer
60
salaries
| ₹6.5 L/yr - ₹18.8 L/yr |
Engineer
40
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| ₹4 L/yr - ₹10.8 L/yr |
Senior Software Engineer
33
salaries
| ₹8.5 L/yr - ₹22.2 L/yr |
AI Engineer
29
salaries
| ₹5 L/yr - ₹11 L/yr |
Staff Engineer
29
salaries
| ₹14.4 L/yr - ₹32 L/yr |
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