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Bitsilica
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I applied via Walk-in and was interviewed in Jan 2024. There was 1 interview round.
posted on 3 Mar 2024
I was interviewed in Feb 2024.
They had given 35question which contain aptitude 5Q,verilog 10 codes & theory , sv codes and theory and uvm question. 2nd round they they took interview based on our resume. They rejected .
posted on 10 Feb 2024
I applied via Referral and was interviewed before Feb 2023. There were 3 interview rounds.
Aptitude test like general questions whivh belongs to work time
Logical Questions in verilog
Bitsilica interview questions for popular designations
Top trending discussions
posted on 31 Oct 2024
I applied via Walk-in and was interviewed in Oct 2024. There were 3 interview rounds.
posted on 21 Nov 2024
I applied via Recruitment Consulltant and was interviewed in Oct 2024. There were 3 interview rounds.
We have 25 questions and negative marking is there
Storage classes in C language define the scope and lifetime of variables.
There are four storage classes in C: auto, register, static, and extern.
Auto variables are local to the block they are declared in and have automatic storage duration.
Register variables are stored in CPU registers for faster access.
Static variables retain their value between function calls.
Extern variables are declared outside of any function and ...
There are 10 address lines present in 1kb memory.
1kb memory = 1024 bytes
To address 1024 bytes, 10 address lines are needed (2^10 = 1024)
Reverse an array of strings
Create a new array to store the reversed strings
Iterate through the original array in reverse order and add each element to the new array
Return the new array as the reversed array
I applied via Referral and was interviewed in Nov 2024. There was 1 interview round.
First was aptitude which had questions on analog, digital, network theory, microcontrollers, general aptitude question which was medium level which I clear & got one to one round. In interview he didn't ask much of interview question 1st question was on academic & design verification project, 2nd was on protocol timing diagram for which the interviewer wanted the exact print of specification sheet where my diagram was a little shabby,which made him upset & didn't continue to ask proper questions .
posted on 16 Jan 2025
posted on 24 Aug 2024
I applied via Campus Placement
Online mode of MCQ in college
Similar to round 1 but offline
Arrays, string, conditional clause
Advanced programming questions from DSA, get help from FAQs and Imp leetcode. Concept explanation is must, partial code is enough
Named as design round, more like framing solution for a problem, will be easy.
Interview experience
based on 36 reviews
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Design & Verification Engineer
52
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| ₹2.8 L/yr - ₹12.9 L/yr |
Embedded Software Engineer
21
salaries
| ₹1.4 L/yr - ₹6 L/yr |
Verification Engineer
8
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| ₹4 L/yr - ₹13 L/yr |
Design Engineer
7
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| ₹5 L/yr - ₹10 L/yr |
RTL Design Engineer
5
salaries
| ₹1.8 L/yr - ₹6 L/yr |
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