Physical Design Engineer - Cadence Virtuoso (3-5 yrs)

We are looking for a skilled and detail-oriented Physical Design Engineer with expertise in PD synthesis and proficiency with Cadence Genus tool. The candidate will contribute to our advanced VLSI design projects, focusing on delivering high-quality RTL-to-GDSII flow solutions. You will work collaboratively with cross-functional teams to ensure seamless implementation and optimization of designs.

Key Responsibilities :

PD Synthesis :

- Perform synthesis of RTL designs using the Genus synthesis tool.

- Optimize the design for area, power, and performance to meet the project specifications.

- Resolve synthesis-related issues, including timing violations and area constraints.

- Generate and validate netlists for further physical design implementation.

Tool Expertise - Genus :

- Configure and manage the Cadence Genus tool for various projects.

- Work on scripting and automation to enhance efficiency in synthesis workflows.

- Conduct detailed analysis of synthesis reports and logs to troubleshoot and improve design quality.

Project Modules :

- Collaborate with teams working on modules like:

- High-speed interfaces (e.g., PCIe, DDR).

- Processor cores (ARM, RISC-V, etc.).

- Signal processing blocks and custom accelerators.

- Analog-mixed signal designs.

Cross-functional Collaboration :

- Work closely with RTL designers to ensure accurate design handoff.

- Collaborate with backend teams for seamless physical implementation.

- Interface with verification and DFT teams to ensure design testability and functionality.

Documentation and Reporting :

- Maintain clear and detailed documentation of synthesis flows, constraints, and processes.

- Provide periodic status updates and insights to project stakeholders.

Qualifications :

- Bachelor's/Master's degree in Electronics Engineering, Computer Engineering, or a related field.

- Strong expertise in RTL synthesis using the Cadence Genus tool.

- Hands-on experience with physical design flows, including timing closure and power optimization.

- Solid understanding of design constraints (SDC) and STA principles.

- Proficiency in scripting languages like Tcl, Perl, or Python.

Preferred Skills :

- Familiarity with tools such as Innovus and Virtuoso.

- Experience with chip tapeout processes.

- Knowledge of standard cell libraries, IO pads, and memory compilers.

- Excellent problem-solving and communication skills.

- Project Scope and Work Environment:

- Opportunity to work on cutting-edge modules used in advanced semiconductor applications.

- Exposure to end-to-end chip design processes.

- Collaborative work culture with a focus on innovation and continuous learning.