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3 Perfect Job Accord Jobs

ASIC Design Engineer - VHDL/System Verilog (5-8 yrs)

5-8 years

ASIC Design Engineer - VHDL/System Verilog (5-8 yrs)

Perfect Job Accord

posted 1mon ago

Job Description

About the Role :


We are seeking a highly motivated and experienced ASIC Design Engineer to join our growing team in Hyderabad. The ideal candidate will have a strong background in digital logic design, verification, and implementation. You will be responsible for contributing to the design and development of cutting-edge ASICs, working through all phases of the design cycle, from specification to tapeout.

Responsibilities :


- Design and implement digital circuits using Verilog, VHDL, or SystemVerilog.

- Perform RTL verification using industry-standard simulation tools (i.e., VCS, QuestaSim, ModelSim).

- Utilize synthesis tools (i.e., Synopsys Design Compiler, Cadence Genus) for logic synthesis and optimization.

- Develop and execute test plans for functional verification.

- Perform static timing analysis (STA) and closure.

- Collaborate with other engineers to integrate designs into larger systems.

- Participate in design reviews and contribute to improving design methodologies.

- Debug and troubleshoot design issues.

- Work closely with physical design engineers to ensure successful chip implementation.

- Contribute to the development of specifications and micro-architecture definitions.

- Document design and verification results.

- Stay up-to-date with the latest industry trends and technologies.

Qualifications :


- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 5+ years of proven experience in RTL design and verification.

- Strong understanding of digital logic design principles.

- Proficiency in Verilog, VHDL, or SystemVerilog HDL.

- Hands-on experience with simulation tools (i.e., VCS, QuestaSim, ModelSim).

- Experience with logic synthesis and optimization using industry-standard tools (i.e., Synopsys Design Compiler, Cadence Genus).

- Knowledge of static timing analysis (STA) and timing closure.

- Familiarity with ASIC design flow and methodologies.

- Excellent problem-solving and analytical skills.

- Strong communication and teamwork skills.

Preferred Skills (Optional) :


- Experience with low-power design techniques.

- Knowledge of scripting languages (i.e., Python, Perl).

- Experience with formal verification.

- Familiarity with different bus protocols (i.e., AMBA).

- Experience with FPGA design and prototyping.

- Knowledge of semiconductor fabrication processes


Functional Areas: Other

Read full job description

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Perfect Job Accord Benefits

Free Transport
Child care
Gymnasium
Cafeteria
Work From Home
Free Food +6 more
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