ASIC Design Engineer - Verilog/VHDL (5-8 yrs)

Job Description :

This is what you are responsible for :

- Define micro-architecture and write detailed design specifications.

- Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog.

- Implement complex digital functions and algorithms in RTL.

- Create and execute detailed test plans to verify RTL designs.

- Optimize designs for power, performance, and area (PPA) constraints.

- Perform simulation and debugging to ensure design correctness.

- Work with verification engineers to develop test benches and validate RTL against specifications.

- Strong understanding of digital design principles and concepts.

- Proficiency in writing and debugging RTL code.

- Experience with synthesis, static timing analysis, and linting tools.

- Familiarity with scripting languages such as Python, Perl, or TCL for automation.

- Experience in any of processor subsystem design, interconnect design, high speed IO interface design.

Qualifications :

- Bachelor's or master's degree in computer engineering, or related field.

- 5+ years of experience in RTL design and verification.

- Proven experience with digital logic design using Verilog, VHDL, or SystemVerilog.

- Experience with simulation tools such as VCS, QuestaSim, or similar.

- Hands-on experience with RTL design tools (e.g, Synopsys Design Compiler, Cadence Genus)