Digital Design Verification Engineer (5-8 yrs)

Basic Requirement :

- Strong digital design fundamentals & basic Electrical engineering

- Experience with Verilog, System Verilog languages with UVM methodology.

- Experience on randomization and coverage driven digital verification.

- Experience in working with VIPs, creating TB components, agents, monitors, scoreboards and other ways to automate verification.

- Hand on experience in RTL and Gate level simulations of complex ASIC at block and top level

- Expert in using simulation tools (preferably Cadence, Xcelium/Ncsim).

- Basic scripting knowledge using shell/python/perl.

- Excellent debugging and problem-solving skill.

- Excellent in Coverage driven verification with code coverage, functional coverage

- Experience in Formal verification (using Jasper Gold) is good to have

- Good communication, presentation skills and teamwork.

Primary Responsibilities :

- Responsible to develop detailed coverage driven Verification plan working closing with System and Application team and design team.

- Owning part of digital verification of the sub-system and full-chip by working closely with other verification team members, leads including outside services.

- Develop/Enhance SV/UVM based testbenches and tests and simulations at all phases (RTL, GLS),

- Understanding spec and coming up with testplan. Writing TB components, testcases, checkers, assertions, enhancing with randomization and coverage-feedbacks.

- RTL and GLS regression and follow-up with tracking of the various activities. Run coverage and meet the defined coverage(coverage & functional) goals.

- Good interaction with Digital Design team, Firmware developers, Analog Designers, and rest of the team.

- Excellent teamwork, adapting to situations and ability to guide, help DV members Communication of DV status, issues, and concerns.

- Innovate & drive new and improved design verification methodologies where needed, work with the EDA team to upgrade tools and flows.

- Interacting with Test/Silicon Validation/Application Engineering team to ensure successful use of products and support customer applications debug/analysis.

- Identify and write all types of coverage measures for stimulus and corner-cases.

- Debug tests with design engineers to deliver functionally correct design blocks.

- Close coverage measures to identify verification holes and to show progress towards tape-out.

Preferred Qualifications :

- Demonstrated strong analytical and problem-solving skills.

- Effective communication skills to interact with all stakeholders.

- Ability to work in teams and collaborate effectively with people in different functions.

- Strong time management skills that enable on-time project delivery.

- Ability to work effectively in a fast-paced and rapidly changing environment.

- Ability to take the initiative and drive for results.

- Ability to build strong, influential relationships with cross-functional teams.

Added Advantage :

- Experience in silicon debug along with design and silicon validation team.

- Experience in audio signal processing and understanding of audio systems/applications.

- Hands-on exp on I2C, SPI, ASI protocols.

- Hand on experience on Cadence tools