Design & Verification Engineer - System Verilog/UVM (5-7 yrs)

Job Description :

The ideal candidate will have extensive experience in SystemVerilog (SV) and Universal Verification Methodology (UVM), with a strong background in developing and modifying UVM testbenches (TBs), creating and executing test plans, and ensuring high levels of functional and code coverage.

Responsibilities :

- Develop and maintain UVM testbenches for various projects.

- Write and modify UVM tests based on project requirements.

- Create detailed test plans and develop tests according to the plans.

- Perform simulation, debugging, and regression testing.

- Ensure functional and code coverage targets are met.

- Utilize assertions to enhance verification quality.

- Collaborate with cross-functional teams to deliver high-quality verification solutions.

Qualifications :

- Bachelor's or Master's degree in Engineering (B.Tech/B.E) or related field.

- 5+ years of industry experience in design and verification.

- Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM).

- Experience in developing UVM testbenches and writing/modifying UVM tests.

- Proven ability to create and execute comprehensive test plans.

- Expertise in simulation, debugging, and regression testing.

- Solid experience in functional and code coverage analysis.

- Familiarity with using assertions in verification processes.

Skills :

- Excellent problem-solving and analytical skills.

- Strong communication and teamwork abilities.

- Attention to detail and commitment to high-quality work.