ASIC/Verification Engineer - System Verilog (5-8 yrs)

Location : Hyderabad, India

Experience : 5+ Years

Notice Period : Up to 45 Days

About the Job :

We are seeking a highly motivated and experienced ASIC Design and Verification Engineer to join our growing team.

As a key member of our hardware engineering group, you will be responsible for the design, verification, and implementation of complex digital circuits for our cutting-edge products.

You will work closely with architects, designers, and other engineers to deliver high-quality, robust, and power-efficient designs.

Responsibilities :

- Participate in the full ASIC design cycle, from specification development to post-silicon validation.

- Design and implement RTL (Register-Transfer Level) using Verilog, VHDL, or System Verilog.

- Develop and execute verification plans, testbenches, and test cases using System Verilog and UVM (Universal Verification Methodology).

- Perform functional verification, coverage analysis, and bug debugging using industry-standard simulation tools (e. VCS, QuestaSim, or similar).

- Utilize synthesis tools (e., Synopsys Design Compiler, Cadence Genus) to generate gate-level netlists.

- Perform static timing analysis (STA) and address timing closure issues.

- Collaborate with physical design engineers to ensure successful implementation of the design.

- Contribute to the development and improvement of design and verification methodologies.

- Participate in code reviews and provide constructive feedback.

- Work closely with cross-functional teams, including architects, hardware engineers, and software engineers.

- Document design and verification results clearly and concisely.

Required Skills and Experience :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 5+ years of proven experience in RTL design and verification.

- Strong understanding of digital logic design principles and concepts.

- Proficiency in Verilog, VHDL, or SystemVerilog HDL.

- Hands-on experience with industry-standard simulation tools (e., VCS, QuestaSim, or similar).

- Experience with RTL design and synthesis tools (e., Synopsys Design Compiler, Cadence Genus).

- Knowledge of verification methodologies, including UVM.

- Experience with coverage-driven verification and constraint randomization.

- Familiarity with scripting languages (e., Python, Perl) is a plus.

- Strong analytical and problem-solving skills.

- Excellent communication and teamwork skills.

- Ability to work independently and as part of a team.

Preferred Skills (Optional) :

- Experience with low-power design techniques.

- Knowledge of ASIC design flow and methodologies.

- Experience with formal verification.

- Familiarity with different bus protocols (e., AMBA, AXI).

- Experience with post-silicon validation