Senior Design Verification Engineer - System Verilog/UVM (5-10 yrs)

Design Verification Leader

Company : Leadsoc Technologies

Experience : 5-10 years

About the Role :

Leadsoc Technologies is seeking a highly skilled and experienced Design Verification Leader to join our dynamic team. In this role, you will be responsible for leading and executing complex verification projects, ensuring the quality and functionality of cutting-edge digital designs.

Responsibilities :

- Develop and execute comprehensive verification plans and testbenches using SystemVerilog and UVM methodologies.

- Perform independent verification tasks for IP blocks and full chip designs.

- Analyze and debug complex design issues, working closely with design engineers to identify and resolve root causes.

- Develop and maintain verification environments and test suites.

- Contribute to the continuous improvement of verification methodologies and processes.

- Mentor junior engineers and provide technical guidance.

- Stay abreast of the latest advancements in verification technologies and methodologies.

Qualifications :

- 5-10 years of experience in digital design verification.

- Strong proficiency in SystemVerilog and UVM methodologies.

- Experience with IP and/or SoC verification.

- Excellent analytical and problem-solving skills.

- Strong communication and collaboration skills.