Mempage Technologies - IP Verification Engineer - UVM & System Verilog Methodologies (5-8 yrs)

We are seeking a skilled and experienced IP Verification Engineer to join our team.

The ideal candidate will have a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM) with hands-on experience in building and maintaining complex verification environments for IP-level projects.

The role involves developing robust testbenches, creating detailed verification plans, and debugging complex hardware designs.

Key Responsibilities :

- Develop, implement, and maintain SystemVerilog UVM-based testbenches for IP verification.

- Collaborate with design and architecture teams to understand IP specifications thoroughly.

- Build reusable components such as Driver, Monitor, Scoreboard, Reference Models, and Sequences.

- Design and implement verification scenarios and test cases to validate the functionality of the IP under test.

- Prepare comprehensive verification plans based on IP specifications and project requirements.

- Define coverage goals and metrics, ensuring alignment with overall verification objectives.

- Employ advanced debugging techniques to identify and resolve issues in design and verification environments.

- Collaborate closely with RTL designers to analyze and debug test failures.

- Analyze code and functional coverage metrics to identify gaps in testing.

- Work towards achieving 100% functional and code coverage.

- Continuously optimize verification strategies and frameworks to improve efficiency and reliability.

- Contribute to the development of verification methodologies and best practices.

Required Skills and Qualifications :

- 5-8 years of experience in IP verification using SystemVerilog and UVM.

- Strong understanding of SystemVerilog and UVM principles and methodologies.

- Hands-on experience in developing complete testbenches, including Driver, Monitor, Scoreboard, Reference Models, Sequences, and Test Cases.

- Proficient in debugging techniques and tools such as waveform viewers, simulation logs, and assertions.

- Proven track record in creating verification plans and achieving high-quality results.

- Strong understanding of functional coverage, code coverage, and their application in verification.

- Excellent problem-solving and analytical skills.

- Strong written and verbal communication skills for effective collaboration.

- Ability to work in a fast-paced environment with minimal supervision.

- Experience with scripting languages such as Python, Perl, or TCL for automation.

- Familiarity with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).

- Knowledge of low-power or high-speed IP verification methodologies.

- Opportunity to work on cutting-edge IP verification projects.

- Collaborative and innovative work environment.

- Competitive compensation and benefits package.

- Career growth opportunities and continuous learning initiatives.