AMS Verification Engineer - UVM/Cadence Virtuoso (7-14 yrs)

Job Description :

As an AMS Verification Engineer, you will play a crucial role in ensuring the quality and reliability of analog and mixed-signal (AMS) integrated circuits.

You will be responsible for developing and executing verification methodologies, writing testbenches, and performing simulations to validate the design's functionality and performance.

Key Responsibilities :

- Define and implement verification methodologies, including test plan creation, testbench development, and coverage-driven verification.

- Utilize industry-standard HVL languages like SystemVerilog (SV) and Universal Verification Methodology (UVM).

- Develop comprehensive testbenches to cover all aspects of the design, including functional, timing, and power verification.

- Write constrained-random verification (CRV) tests to achieve high coverage.

- Perform simulations using simulators like Cadence Virtuoso and Synopsys PrimeSim.

- Verify signal integrity aspects, including timing, noise, and power consumption.

- Utilize tools like Cadence Virtuoso and Synopsys PrimeTime for signal integrity analysis.

- Perform low-power verification, including power estimation and power reduction techniques.

- Analyze power consumption and identify optimization opportunities.

- Collaborate with other verification engineers to share knowledge and best practices.

Required Skills and Experience :

- Strong understanding of analog and mixed-signal circuit design principles.

- Proficiency in Verilog and SystemVerilog.

- Experience with industry-standard verification methodologies (UVM).

- Knowledge of simulation tools like Cadence Virtuoso and Synopsys PrimeSim.

- Understanding of signal integrity and low-power design techniques.

- Strong problem-solving and analytical skills.

- Excellent communication and teamwork skills