14 Meraqui Jobs
5-10 years
AMS Verification Engineer - UVM/System Verilog (5-10 yrs)
Meraqui
posted 1mon ago
Job Description :
- Grounds up verification environment development using SV/ UVM is a must
- One of the Serdes of high speed protocols like PCIe or USB 3 or MIPI
- Testplanning, AMS Setup, Experience in wreal, RNM, Verilog A
- VCS Primesim AMS and Primesim XA tool
- Experience in wreal, RNM, Verilog A, exp in System Verilog and UVM
- 4 to 12 years of experience in AMS verification
- Understanding of Analog blocks/ behavior is a must
- Should be able to understand and debug RNM, wreal, Verilog ams models
- Analog modeling experience using RNM, wreal, Verilog ams is a big plus
- Experience in AMS verification using SV/ UVM is a must
- Experience in 'C' based verification is a plus
Functional Areas: Other
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