Cadence Design Systems - Product Engineer - Synopsys (4-7 yrs)

Job Summary :

We are seeking a highly skilled and motivated Product Engineer with 4-7 years of experience to join our team.

The ideal candidate will have a strong understanding of GLS (Gate-Level Simulation) challenges and SDC (Synopsys Design Constraints) constraints, including MCP (Multi-Corner Power) and FP (Floorplan) considerations.

This role requires strong technical expertise and the ability to analyze and solve design and implementation challenges in the product development lifecycle.

Key Responsibilities :

- Address and resolve GLS challenges related to design verification and debugging at the gate level.

- Work with SDC constraints to ensure proper timing, optimization, and coverage across various design corners, focusing on MCP/FP constraints.

- Collaborate with cross-functional teams including RTL design, physical design, and verification to ensure successful product delivery.

- Analyze and debug issues related to timing, power, and signal integrity in complex SoC designs.

- Develop and maintain scripts/tools for automation to improve productivity in GLS and SDC workflows.

- Drive technical discussions to identify gaps, propose solutions, and ensure optimal design practices are followed.

- Support silicon bring-up and validation phases to resolve functional and performance issues.

Technical Expertise :

- Strong understanding of GLS (Gate-Level Simulation) and the associated debugging process.

- In-depth knowledge of SDC constraints and their impact on timing, power, and design optimization.

- Familiarity with Multi-Corner Power (MCP) and Floorplan (FP) constraints.

Tools & Technologies :

- Hands-on experience with tools like Synopsys, Cadence, or Mentor Graphics for simulation and verification.

- Proficiency in scripting languages (e.g , Python, TCL, Perl) for automation and tool customization.

- Experience with EDA tools for timing analysis, synthesis, and STA (Static Timing Analysis).

Other Skills :

- Strong debugging and problem-solving skills in SoC design and implementation.

- Ability to work in a collaborative and dynamic environment.

- Excellent communication and interpersonal skills.

Preferred Qualifications :

- Prior experience in high-performance SoC design or ASIC implementation.

- Exposure to low-power design methodologies and techniques.

- Knowledge of DFT (Design for Testability) and related constraints