Sivaltech Senior Physical Design Engineer Interview Questions and Answers

Apptitide, Digital Electronics, physical Design concepts.

Q1. 1.Self Introduction, Hobbies 2.PD Project in detail 3.Timing arc of Latch, Flipflop 4.Library setup time 5.Temperature Inversion mathematical in detail 6.HVT, LVT cells 7.NDR rules 8.How to fix setup, hol...read more
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Q1. What are the PD inputs and outputs
Ans. 
PD inputs are design specifications and constraints, while outputs are physical layout of the design.
• Inputs include design specifications, constraints, technology libraries, and floorplan.

• Outputs include physical layout, placement of components, routing of wires, and design verification.

• Example: Input - RTL design, clock frequency, power constraints. Output - GDSII layout, timing analysis report.
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Q2. Describe each stage of PNR flow
Ans. 
PNR flow consists of synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff stages.
• Synthesis: Convert RTL code to gate-level netlist

• Floorplanning: Define chip area, core, and I/O locations

• Placement: Place gates in specific locations to meet timing constraints

• Clock tree synthesis: Create clock distribution network

• Routing: Connect gates with wires while considering timing and congestion

• Signoff: V...read more
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Q3. What are the different techniques to minimize congestion?
Ans. 
Techniques to minimize congestion include buffer insertion, wire spreading, and layer assignment.
• Buffer insertion: Adding buffers to critical paths to improve timing and reduce congestion.

• Wire spreading: Distributing wires evenly to reduce congestion in specific areas.

• Layer assignment: Properly assigning different signal layers to reduce congestion on a single layer.
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Q4. What is the setup and hold time and different techniques to fix the setup and hold time violations?
Ans. 
Setup and hold time are timing constraints in digital circuits. Techniques to fix violations include adjusting clock skew, buffering signals, and optimizing routing.
• Setup time is the minimum amount of time a data input must be stable before the clock edge for proper operation.

• Hold time is the minimum amount of time a data input must be stable after the clock edge for proper operation.

• Techniques to fix setup and hold ti...read more
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Q5. What is signal integrity?
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Signal integrity refers to the quality of an electrical signal as it travels through a circuit or system.
• It involves ensuring that the signal remains clear and undistorted from the transmitter to the receiver.

• Factors affecting signal integrity include impedance matching, noise, crosstalk, and reflections.

• Signal integrity analysis is crucial in high-speed digital design to prevent data errors and ensure reliable communi...read more
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Q6. What is crosstalk and noise and how to fix it?
Ans. 
Crosstalk is unwanted interference between signals on adjacent lines, while noise is random unwanted signals that can degrade performance.
• Crosstalk occurs when signals on adjacent lines interfere with each other due to coupling effects.

• Noise is random unwanted signals that can be caused by various sources such as electromagnetic interference or power supply fluctuations.

• To fix crosstalk, techniques like spacing out lin...read more
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Q7. What is clock latency, skew and jitter?
Ans. 
Clock latency is the delay between the clock signal being generated and reaching the destination, skew is the variation in arrival times of the clock signal at different destinations, and jitter is the variation in the period of the clock signal.
• Clock latency is the delay between the clock signal being generated and reaching the destination.

• Skew is the variation in arrival times of the clock signal at different destina...read more
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Q8. What is useful skew, negative skew and positive skew?
Ans. 
Useful skew, negative skew, and positive skew are terms used in physical design to describe timing constraints.
• Useful skew refers to intentional delay added to certain paths to meet timing requirements.

• Negative skew occurs when data arrives later than expected, leading to potential timing violations.

• Positive skew occurs when data arrives earlier than expected, potentially causing setup time violations.

• Skew can be adjus...read more
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Q1. Regarding verification uvm
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Q2. About projects and clients
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Very basic questions on digital and verilog and sv

Q1. About latches and flip flops
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Q2. Diff bw latches and ff
Ans. 
Latches are level-sensitive while flip-flops are edge-triggered. Flip-flops have a clock input while latches do not.
• Latches are level-sensitive, meaning the output changes as long as the enable signal is active.

• Flip-flops are edge-triggered, meaning the output changes only on the rising or falling edge of the clock signal.

• Flip-flops have a clock input which latches do not have.

• Latches are faster but consume more power ...read more
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Q3. What is digital electronics
Ans. 
Digital electronics is a branch of electronics that deals with digital signals and systems.
• Deals with discrete values (0s and 1s)

• Utilizes logic gates to process digital signals

• Used in computers, smartphones, digital cameras, etc.

• Digital circuits can be easily replicated and manipulated
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Assignment related to battery design for a given conditions

What government policies can be implemented for circular economy?

Q1. Introduction followed with internship and how you got in to that particular stream.
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Q2. Resume drilling and concepts related to your branch.
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Digital Verilog and Sv and aptitude

Q1. What is digital electronics
Ans. 
Digital electronics is a branch of electronics that deals with digital signals and systems.
• Deals with discrete values (0s and 1s)

• Utilizes logic gates to perform operations

• Commonly used in computers, calculators, and digital clocks
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Q2. Difference between latch and flipflops
Ans. 
Latches are level-sensitive while flip-flops are edge-triggered. Flip-flops have a clock input while latches do not.
• Latches are level-sensitive, meaning the output changes as long as the enable signal is active. Flip-flops are edge-triggered, changing only on the rising or falling edge of the clock signal.

• Flip-flops have a clock input which controls when the output changes, while latches do not have a clock input.

• Latch...read more
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Q1. Are you ok with bond
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Q2. Will you relocate
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