Sivaltech Interview Questions and Answers

Q1. Details of UVM and System Verilog blocking and non blocking assignment
Ans. 
UVM is a methodology for verifying complex designs using SystemVerilog. Blocking assignments execute sequentially, while non-blocking assignments execute concurrently.
• UVM (Universal Verification Methodology) is a standardized methodology for verifying complex designs in SystemVerilog.

• Blocking assignments in SystemVerilog execute sequentially, meaning the next statement waits for the current statement to finish.

• Non-bloc...read more
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Q1. Where do you see yourself in 5 years and strength and weakness
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Q1. Ofdm, equalization, estimation
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Q1. Ofdm, equalization, estimation
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Q1. Discuss 4 case study related to supply chain management.
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Round duration - 140 minutes
Round difficulty - Medium

Test timing was at 2:00 pm , it was conducted in a college and the environment was good for the test. Camera was a primary part of test, so no suspicious activity.

Q1. 
Sum of Two Numbers Represented as Arrays
Given two numbers in the form of two arrays where each element of the array represents a digit, calculate the sum of these two numbers and return this sum as an ar...read more
Ans. 
Given two numbers represented as arrays, calculate their sum and return the result as an array.
• Iterate through the arrays from right to left, adding digits and carrying over if necessary

• Handle cases where one array is longer than the other by considering the remaining digits

• Ensure the final sum array does not have any leading zeros
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Round duration - 20 minutes
Round difficulty - Easy

The round was conducted at around 12 p.m. I was called at the college location and then it was conducted. The interviewer was quite polite and frank.

Round duration - 8 minutes
Round difficulty - Easy

This round was conducted right after finishing and clearing the technical round at the same place and on the same day.