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I applied via Company Website and was interviewed in May 2024. There was 1 interview round.
Sequence detector is a digital circuit that detects a specific sequence of bits in a stream of input data.
FSM (Finite State Machine) is commonly used to design sequence detectors.
RTL (Register Transfer Level) describes the behavior of digital circuits using registers and logic gates.
Example: A sequence detector that detects '1010' in a stream of binary data.
Example: FSM states for this detector could be S0, S1, S2, S3
I applied via Company Website and was interviewed in Sep 2024. There were 2 interview rounds.
C++ on leetcode programming
Verify last level cache by running stress tests, analyzing cache hit/miss rates, and comparing performance metrics.
Run stress tests to simulate high load scenarios and observe cache behavior
Analyze cache hit/miss rates to ensure data is being efficiently stored and retrieved
Compare performance metrics before and after cache verification to measure improvements
Use tools like CacheGrind or Valgrind for detailed cache ana
Identifying and fixing a race condition in a multi-threaded system
Observed intermittent failures in test results
Used debugging tools like gdb and log analysis to trace the issue
Identified the root cause as a race condition between two threads
Implemented a mutex lock to resolve the issue
Verified the fix by running stress tests
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I was interviewed before Jul 2016.
I was interviewed before Sep 2016.
I applied via Recruitment Consultant and was interviewed before Sep 2018. There were 4 interview rounds.
based on 3 interviews
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