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Rivos

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6 Rivos Jobs

Silicon Electrical Analysis & Signoff TLM

Rivos Inc.

3-7 years

Bangalore / Bengaluru

1 vacancy

Rivos

posted 5d ago

Job Role Insights

Key skills for the job

Python Automation Testing AutoCAD Packaging Semiconductor Partnerships

+ 4 more

Job Description

About the Role

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon EMIR Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

This role involves performing detailed electromigration (EM) and IR drop (IR) analysis to ensure the reliability and robustness of semiconductor designs. The ideal candidate will work closely with logic design, verification, and physical implementation teams to identify and resolve potential power integrity and signal reliability issues.

Responsibilities

Develop our Electrical Analysis methodology and infrastructure to enable the verification flow of large HPC SoCs.
Be responsible for FC EMIR signoff quality that meets or exceeds PPA targets.
Perform full chip analysis debug and closure of all EA flows, including IR, IVD, EM for signal and power.
Provide input to full chip floorplan and guidance to the implementation teams throughout the project to enable early convergence and final closure.
Collaborate cross-functionally with Physical design team, Technology team and CAD partners to drive closure targets and signoff criteria.
Participate in design and validation of Power Distribution Networks optimized for best PPA in specific IPs.
Manage, staff, mentor a team of EMIR engineers across geographies.

Requirements

Experience with industry standard EMIR EDA tools (Apache Redhawk, Cadence Voltus)
Understanding of package modeling techniques for full level power analysis.
Expertise in convergence issues associated with high performance designs in advanced process nodes (static and dynamic IR driven timing closure).
Strong scripting skills in tcl and python.
Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills.
Self starter and highly motivated.
Ability to work cross-functionally with various teams and be productive under aggressive schedules.
Experience in FC EMIR design convergence of a large chip in advanced technologies.
Experience managing a team of engineers across geographies.

Education and Experience

PhD, Master s Degree in EE, EECS

Experience :

Required : 15+ years of experience in EMIR analysis in chip design.
Preferred : Experience with advanced technology nodes (e.g., 5nm, 3nm).

Skills and Competencies

Strong knowledge of electromigration , IR drop , and power grid design principles.
Hands-on experience with tools like ANSYS RedHawk , Cadence Voltus , or equivalent.
Proficiency in scripting languages such as Python , TCL , or Perl for automation.
Familiarity with physical design flows (floorplanning, placement, routing ).
Understanding of advanced packaging technologies and their impact on power integrity.
Excellent analytical and problem-solving skills with attention to detail.
Strong communication skills to effectively present findings and solutions.

Why Join Us

Opportunity to work on cutting-edge semiconductor technology and advanced nodes.
Collaborative and innovative work environment with cross-functional exposure.
Competitive compensation and benefits package.
Career growth opportunities in a leading chip design organization.

Employment Type: Full Time, Permanent

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