Qualcomm Physical Design Engineer Interview Questions and Answers

Q1. About Master's thesis
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Q2. CTS strategy, a puzzle question, STA problems
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Q1. Floorplan strategies to calculate maximum macro counts that can be used in a block, placement constraints, congestion issues.
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Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.
• Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.

• Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.

• Congestion issues arise when there is limited space or resources avai...read more
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Q2. Multi cycle paths, timing violations in reg2reg path.
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Q3. Routing issues, signal integrity, IR drop analysis.
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Q4. Logical DRC's, causes and fixing strategies.
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Q1. Issues and fixes faced during previous projects.
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Q2. Placement, CTS, CMOS concepts
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Q3. LVS, Design for manufacturing.
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Q1. Toggle the bits of given input
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Toggle the bits of given input
• Create a mask with all bits set to 1

• XOR the input with the mask to toggle the bits

• Repeat the process for each bit position
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Q2. Clear the set bit
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Q1. Print the star pattern
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Print a star pattern using loops
• Use nested loops to print the desired pattern

• Increment the number of stars in each row to create the pattern

• Example: for a pattern with 5 rows - * , ** , *** , **** , *****
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Q2. Microprocessor microcontroller topics are asked
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Q1. Assertions and coverage
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Q2. Umv basic principle
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UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
• UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

• It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

• UVM encourages the use of constrained-random stimulus generation and coverage-driven ...read more
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Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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40 aptitude qns and some mcqs on basic programming

Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
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Q2. Two sum- return true or false
Ans. 
Given an array of integers, determine if there are two numbers that add up to a specific target.
• Iterate through the array and store each element in a hash set.

• For each element, check if the difference between the target and the element exists in the hash set.

• If the difference exists, return true; otherwise, continue iterating.

• Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
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Q3. Merge sort function code
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Q4. Palindromic string or not
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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