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I applied via LinkedIn and was interviewed in Nov 2024. There was 1 interview round.
I applied via LinkedIn and was interviewed before Dec 2023. There was 1 interview round.
I applied via Campus Placement and was interviewed in Jan 2016. There were 3 interview rounds.
Reduction of 3D Kmap involves simplifying a 3D truth table to minimize the number of logic gates required.
3D Kmap is a graphical representation of a truth table with three variables
Reduction involves grouping adjacent cells with the same output value
The goal is to minimize the number of groups and variables in each group
Simplification can be done using Boolean algebra or Karnaugh maps
Example: Reducing a 3D Kmap with in
A design engineer is responsible for creating and developing innovative designs for products or systems.
Designing and prototyping new products
Collaborating with cross-functional teams to ensure design feasibility
Using CAD software to create detailed drawings and specifications
Testing and evaluating prototypes to ensure functionality and performance
Making design improvements based on feedback and testing results
posted on 28 Aug 2016
I applied via Campus Placement
posted on 26 Jun 2024
I applied via LinkedIn and was interviewed in May 2024. There was 1 interview round.
Code for constraints
Code for driver
I applied via Referral and was interviewed before Jun 2023. There were 2 interview rounds.
Design a micro arch for a given problem
Identify the specific problem that the micro arch needs to solve
Consider the size and scale of the micro arch in relation to the problem
Design the structure of the micro arch to efficiently address the problem
Ensure that the materials used are suitable for the intended purpose
Verilog code for micro architecture design
Define modules for different components of the micro architecture
Implement data paths and control logic using Verilog
Use registers, multiplexers, and other logic gates to design the micro architecture
Test the functionality of the micro architecture using simulation tools
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