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DIGICOMM Semiconductor
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I applied via Approached by Company and was interviewed in Apr 2023. There were 2 interview rounds.
PD inputs are design specifications and constraints, while outputs are physical layout of the design.
Inputs include design specifications, constraints, technology libraries, and floorplan.
Outputs include physical layout, placement of components, routing of wires, and design verification.
Example: Input - RTL design, clock frequency, power constraints. Output - GDSII layout, timing analysis report.
PNR flow consists of synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff stages.
Synthesis: Convert RTL code to gate-level netlist
Floorplanning: Define chip area, core, and I/O locations
Placement: Place gates in specific locations to meet timing constraints
Clock tree synthesis: Create clock distribution network
Routing: Connect gates with wires while considering timing and congestion
Signoff: V...
Techniques to minimize congestion include buffer insertion, wire spreading, and layer assignment.
Buffer insertion: Adding buffers to critical paths to improve timing and reduce congestion.
Wire spreading: Distributing wires evenly to reduce congestion in specific areas.
Layer assignment: Properly assigning different signal layers to reduce congestion on a single layer.
Setup and hold time are timing constraints in digital circuits. Techniques to fix violations include adjusting clock skew, buffering signals, and optimizing routing.
Setup time is the minimum amount of time a data input must be stable before the clock edge for proper operation.
Hold time is the minimum amount of time a data input must be stable after the clock edge for proper operation.
Techniques to fix setup and hold ti...
Signal integrity refers to the quality of an electrical signal as it travels through a circuit or system.
It involves ensuring that the signal remains clear and undistorted from the transmitter to the receiver.
Factors affecting signal integrity include impedance matching, noise, crosstalk, and reflections.
Signal integrity analysis is crucial in high-speed digital design to prevent data errors and ensure reliable communi...
Crosstalk is unwanted interference between signals on adjacent lines, while noise is random unwanted signals that can degrade performance.
Crosstalk occurs when signals on adjacent lines interfere with each other due to coupling effects.
Noise is random unwanted signals that can be caused by various sources such as electromagnetic interference or power supply fluctuations.
To fix crosstalk, techniques like spacing out lin...
Clock latency is the delay between the clock signal being generated and reaching the destination, skew is the variation in arrival times of the clock signal at different destinations, and jitter is the variation in the period of the clock signal.
Clock latency is the delay between the clock signal being generated and reaching the destination.
Skew is the variation in arrival times of the clock signal at different destina...
Useful skew, negative skew, and positive skew are terms used in physical design to describe timing constraints.
Useful skew refers to intentional delay added to certain paths to meet timing requirements.
Negative skew occurs when data arrives later than expected, leading to potential timing violations.
Positive skew occurs when data arrives earlier than expected, potentially causing setup time violations.
Skew can be adjus...
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I applied via Campus Placement
posted on 18 Sep 2023
I applied via Naukri.com and was interviewed in Aug 2023. There were 4 interview rounds.
Kaizen is a Japanese term for continuous improvement, while suggestion refers to ideas or proposals for improvement.
Kaizen focuses on making small, incremental improvements in processes or systems
Suggestion involves offering ideas or proposals for improvement to enhance efficiency or quality
Kaizen and suggestion are key components of continuous improvement initiatives in organizations
Examples of kaizen include implemen...
OEE (Overall Equipment Effectiveness) is a measure of how well a manufacturing process is performing.
OEE is calculated by multiplying Availability, Performance, and Quality percentages.
Availability is the ratio of actual production time to planned production time.
Performance is the ratio of actual production speed to ideal production speed.
Quality is the ratio of good units produced to total units produced.
OEE provides...
PPLH improvement refers to the process of improving productivity, profitability, lead time, and quality in a manufacturing setting.
PPLH stands for Productivity, Profitability, Lead Time, and Quality in a manufacturing process.
Improving PPLH involves optimizing production processes, reducing waste, enhancing efficiency, and ensuring high product quality.
Examples of PPLH improvement strategies include implementing lean m...
5S is a methodology for organizing a workplace for efficiency and effectiveness. Shop floor refers to the area where production or manufacturing takes place.
5S stands for Sort, Set in Order, Shine, Standardize, and Sustain.
It involves organizing the workplace to eliminate waste, improve efficiency, and ensure safety.
Examples include labeling tools and equipment, creating designated storage areas, and implementing regul...
TPM stands for Total Productive Maintenance and TQM stands for Total Quality Management.
TPM focuses on maximizing the efficiency of equipment and machinery to prevent breakdowns and defects.
TQM focuses on improving the quality of products and processes through continuous improvement and customer satisfaction.
Both TPM and TQM aim to optimize production processes and reduce waste.
Examples of TPM activities include regula...
Rejection analysis involves identifying and addressing the root causes of rejected products or processes.
Identify the specific reasons for rejection, such as defects in materials, design flaws, or manufacturing errors
Collect data and analyze trends to determine common issues leading to rejection
Implement corrective actions to address the root causes and prevent future rejections
Monitor the effectiveness of the correcti...
IV characteristics of CMOS inverter show the relationship between input voltage and output current.
CMOS inverter has two transistors - NMOS and PMOS connected in series.
For low input voltage, NMOS is ON and PMOS is OFF, resulting in low output voltage.
For high input voltage, NMOS is OFF and PMOS is ON, resulting in high output voltage.
The transition between low and high output voltage occurs at the threshold voltage.
Th...
Set up time and hold time are timing requirements in digital circuits to ensure proper operation.
Set up time is the minimum time before the clock edge that the input signal must be stable.
Hold time is the minimum time after the clock edge that the input signal must be maintained stable.
Violating set up time can lead to incorrect data being latched.
Violating hold time can lead to metastability issues.
Examples: In a flip...
C, c++ python and simple aptitude
A CMOS inverter is a type of digital logic gate that switches between high and low voltage levels.
CMOS stands for Complementary Metal-Oxide-Semiconductor
It consists of a PMOS (p-type metal-oxide-semiconductor) and NMOS (n-type metal-oxide-semiconductor) transistor connected in series
When the input is high, the PMOS transistor conducts and the output is low
When the input is low, the NMOS transistor conducts and the outp...
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