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Bitsilica
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They had given 35question which contain aptitude 5Q,verilog 10 codes & theory , sv codes and theory and uvm question. 2nd round they they took interview based on our resume. They rejected .
posted on 3 Mar 2024
I was interviewed in Feb 2024.
I applied via Walk-in and was interviewed in Jan 2024. There was 1 interview round.
posted on 10 Feb 2024
I applied via Referral and was interviewed before Feb 2023. There were 3 interview rounds.
Aptitude test like general questions whivh belongs to work time
Logical Questions in verilog
Bitsilica interview questions for popular designations
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posted on 24 Jul 2024
randc behavior generates random complex numbers with specified distribution
Use randc to generate random complex numbers
Specify distribution using arguments like mean, variance, etc.
Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
posted on 19 Nov 2022
I applied via LinkedIn and was interviewed in May 2022. There were 4 interview rounds.
This round consists of technical test which was focusing on electronics subjects.
posted on 28 Jul 2024
I applied via Job Portal
Flip-flops are sequential logic circuits used to store and manipulate binary data.
Flip-flops are basic building blocks of digital circuits.
They can store a single bit of information, either 0 or 1.
Flip-flops have two stable states: set and reset.
They are used to store and transfer data in sequential circuits.
Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.
I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.
All aptitude topics covered
Implementing an AND gate in behavioral code
Use if statements to check if both inputs are high
Assign the output to high if both inputs are high
Use Verilog or VHDL syntax depending on the language being used
FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.
FF stores data on clock edge, latch stores data as long as enable signal is active
FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)
FF is used for sequential circuits, latch is used for level-sensitive circuits
Example: D flip-flop (FF) vs SR latch
I was interviewed before Aug 2016.
based on 6 interviews
Interview experience
based on 36 reviews
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