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Bitsilica Interview Questions and Answers

Updated 13 Jul 2024

Bitsilica Interview Experiences

Popular Designations

4 interviews found

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Coding Test 

They had given 35question which contain aptitude 5Q,verilog 10 codes & theory , sv codes and theory and uvm question. 2nd round they they took interview based on our resume. They rejected .

Round 2 - Technical 

(2 Questions)

  • Q1. PROJRCT RELATED
  • Q2. UVM RELATED TESTBENCH FLOW

Design & Verification Engineer Interview Questions asked at other Companies

Q1. 1. XOR gate 2. How you compare two 4 bit numbers only using gates. 3. How to rotate the bits and what happens if you rotate 5 times etc like that
View answer (1)
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I was interviewed in Feb 2024.

Round 1 - Technical 

(2 Questions)

  • Q1. Ask the technical questions.
  • Q2. Basic SV and UVM questions.
Round 2 - Technical 

(2 Questions)

  • Q1. Check my coding knowledge.
  • Q2. Constraints, coverage and assertions.

Interview Preparation Tips

Interview preparation tips for other job seekers - I recently Joined Bitsilica Pvt ltd, and my experience has exceeded expectations. The hiring process was smooth and professional, showcasing the company's commitment to efficiency and respect for candidate' time.

Upon joining, I found an inclusive and vibrant work environment that encourages collaboration and innovation. The emphasis on open communication, professional development, and community engagement makes Bitsilica Pvt Ltd and exceptional workplace. Grateful to be part of such a positive and supportive team and company.

Asic Design Verification Engineer Interview Questions asked at other Companies

Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
View answer (2)

Interview Questions & Answers

user image Akhil Akhil

posted on 13 Jul 2024

Interview experience
1
Bad
Difficulty level
Easy
Process Duration
Less than 2 weeks
Result
No response

I applied via Walk-in and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. What is pointer
  • Q2. What is null pointer

Interview Preparation Tips

Topics to prepare for Bitsilica interview:
  • C
Interview preparation tips for other job seekers - basic c questions

Skills evaluated in this interview

Design & Verification Engineer Interview Questions & Answers

user image Hari Naga Sri Pallavi

posted on 10 Feb 2024

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Referral and was interviewed before Feb 2023. There were 3 interview rounds.

Round 1 - Aptitude Test 

Aptitude test like general questions whivh belongs to work time

Round 2 - Coding Test 

Logical Questions in verilog

Round 3 - HR 

(2 Questions)

  • Q1. Project related Questions and technical
  • Q2. General Questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Practice logical Questions , UVM and sv based Questions

Design & Verification Engineer Interview Questions asked at other Companies

Q1. 1. XOR gate 2. How you compare two 4 bit numbers only using gates. 3. How to rotate the bits and what happens if you rotate 5 times etc like that
View answer (1)

Bitsilica interview questions for popular designations

 Design & Verification Engineer

 (2)

 Asic Design Verification Engineer

 (1)

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Write code randc behaviour
  • Ans. 

    randc behavior generates random complex numbers with specified distribution

    • Use randc to generate random complex numbers

    • Specify distribution using arguments like mean, variance, etc.

    • Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2

  • Answered by AI
  • Q2. Functinal coverage
  • Q3. Code coverage related questions
  • Q4. Monitor and scoreboard connections
  • Q5. Project related questions

Skills evaluated in this interview

I applied via LinkedIn and was interviewed in May 2022. There were 4 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

This round consists of technical test which was focusing on electronics subjects.

Round 3 - Technical 

(1 Question)

  • Q1. In this round , questions were asked in digital design , verilog and projects.
Round 4 - HR 

(1 Question)

  • Q1. In this round as usual HR questions were asked.

Interview Preparation Tips

Interview preparation tips for other job seekers - Waste company Mirafra Technologies, they said that we will send offer letters to you within 2 or 3 days then they will not send offer letters and let you keep waiting for months.
In HR interview threy will say you " Best of Luck for future endeavors with Mirafra " but they will not send you offer letters. Hahahahahahha
It is not good for freshers, they are playing with freshers
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Project questions
  • Q2. Sv and uvm basics
Round 2 - One-on-one 

(2 Questions)

  • Q1. Pcie basic questions
  • Q2. SV and UVM basics
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-

I applied via Job Portal

Round 1 - One-on-one 

(1 Question)

  • Q1. 1) Explain flipflops 2) UVM Architecture 3)constraints
  • Ans. 

    Flip-flops are sequential logic circuits used to store and manipulate binary data.

    • Flip-flops are basic building blocks of digital circuits.

    • They can store a single bit of information, either 0 or 1.

    • Flip-flops have two stable states: set and reset.

    • They are used to store and transfer data in sequential circuits.

    • Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.

  • Answered by AI
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

All aptitude topics covered

Round 2 - Technical 

(2 Questions)

  • Q1. And gate code in behavioral
  • Ans. 

    Implementing an AND gate in behavioral code

    • Use if statements to check if both inputs are high

    • Assign the output to high if both inputs are high

    • Use Verilog or VHDL syntax depending on the language being used

  • Answered by AI
  • Q2. Difference between Ff & latch
  • Ans. 

    FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.

    • FF stores data on clock edge, latch stores data as long as enable signal is active

    • FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)

    • FF is used for sequential circuits, latch is used for level-sensitive circuits

    • Example: D flip-flop (FF) vs SR latch

  • Answered by AI

Interview Preparation Tips

Topics to prepare for Wipro Design & Verification Engineer interview:
  • Design
Interview preparation tips for other job seekers - all basics covered

I was interviewed before Aug 2016.

Interview Preparation Tips

Round: General and technical aptitude
Experience: There were questions on basics of programming and general questions on verbal,reasoning and quantitative.
Tips: Time will be short to answer all so keep watch on time

Round: Group Discussion
Experience: They segregated us in to batches and in our team there were 10 members.
Tips: Easy round
Duration: 15 minutes

Round: Telephonic
Experience: They tested my communication skill in that round

College Name: Dhanalakshmi college of engineering

Bitsilica Interview FAQs

How many rounds are there in Bitsilica interview?
Bitsilica interview process usually has 2 rounds. The most common rounds in the Bitsilica interview process are Technical, Coding Test and Aptitude Test.
How to prepare for Bitsilica interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at Bitsilica. The most common topics and skills that interviewers at Bitsilica expect are Design Verification, Embedded Testing, ARM, ASIC Verification and Accounting.
What are the top questions asked in Bitsilica interview?

Some of the top questions asked at the Bitsilica interview -

  1. what is poin...read more
  2. what is null poin...read more
  3. constraints, coverage and assertio...read more

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Bitsilica Interview Process

based on 6 interviews

Interview experience

4.3
  
Good
View more

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Bitsilica Reviews and Ratings

based on 36 reviews

4.3/5

Rating in categories

4.2

Skill development

4.1

Work-life balance

4.1

Salary

4.1

Job security

4.2

Company culture

4.1

Promotions

4.2

Work satisfaction

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