Analog Mixed Signal Design Verification Specialist

Dear All

We, Cyient is hiring for multiple new positions in AMS V: Sr Engineers, Staff Engineer and Leads for End to End Offshore-Onshore model based Global Product R&D Solution from scratch.

Exp Range: 3-12 Yrs
Base Location: Bangalore, Hyderabad & Pune

Key Skills:
BE/B.Tech in ECE /M.Tech in VLSI with 3 to 12 years experience in Analog Mixed Signal Verification
• Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks
• Good experience in Analog Mixed Signal verification simulation tools
• Good experience in System Verilog, UVM methodologies
• Able to train the team members and guide the team in resolving issues
• Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch.
• Good to have Gate level netlist simulation
• Python, Perl, Shell scripting is added advantage.
• Good communication and documentation skills

Interested Applicants, Kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.

Best Regards
Rajani Kant Sharma
Sr Recruiter: End to End Semicon Vertical
Cyient
Bangalore