Design Verification Engineer

Design Verification Engineer.

Exp- 4+yrs

Location- Bangalore, Pune

Roles and Responsibilities

• Proficient in SoC/IP/ASIC/AMS verification .
• Experience in creating a testplan for the blocks owned, testbench development and the delivery ownership is a must .
• Experience in SV/ UVM based environment and testcase writing is a plus.
  Collaborate with cross-functional teams to identify requirements and develop test plans.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
  
  

Interested can share CV sneha.s@acldigital.com

NP- prefer less notice period or serving Notice period.