Senior Engineer: ASIC Design Verification

Dear Applicants

We, Cyient is hiring for Senior Engineer: ASIC Design Verification for Offshore-Onshore Model based Global Product R&D Solution Opportunity.

Base Location: Bangalore & Hyderabad

Experience Range: 5-10 Yrs

Key Skills:

1. Candidate must have strong experience in SOC/ IP Verification Flow from scratch.

2. Candidate must have strong experience in UVM with TB Development from scratch.

3. Must have strong experience in Protocol Stack: AMBA, PCIE, USB, serial protocols (I2C) or ARM based SOC

4. Must have strong experience in Power aware and Gate Level simulations of SOC.

5. Must have worked in Regressions and Debugging the issues of sanity tests of SOC.

6. Must have worked on CDC Bring-up at SOC Level.

Interested ASIC Verification SME's, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.

Thanks and Regards

Rajani Kant Sharma