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I applied via Recruitment Consulltant and was interviewed in Mar 2023. There were 3 interview rounds.
ICG stands for Inter-Chip Global. It is a network that connects multiple chips in a system.
ICG is used to transfer data between different chips in a system
It helps in reducing the number of wires required for communication between chips
ICG can be used in various design aspects such as clock distribution, power management, and data transfer
Example: In a multi-chip system, ICG can be used to transfer clock signals from o
MSCTS can help in achieving better clock distribution and reducing skew at SOC level CTS.
MSCTS (Multi-Source Clock Tree Synthesis) can optimize the clock tree for better skew and jitter performance.
It can also help in reducing power consumption by optimizing the clock network.
MSCTS can handle multiple clock sources and ensure proper synchronization.
It can also help in meeting timing constraints and reducing clock tree ...
Fixing setup and hold time violations simultaneously requires adjusting clock timing and/or data path delays.
Identify the critical path causing the violations
Adjust the clock timing to meet setup and hold requirements
Adjust the data path delays to meet setup and hold requirements
Use tools like static timing analysis and delay calculation to determine necessary adjustments
Iteratively adjust timing and delays until viola
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I applied via Recruitment Consulltant and was interviewed in Sep 2023. There was 1 interview round.
The temperature of the design I worked on was optimized to ensure proper functionality and reliability.
The temperature was carefully controlled to prevent overheating and ensure performance.
Thermal analysis was conducted to determine the optimal operating temperature.
Cooling solutions such as heat sinks or fans were implemented to manage heat dissipation.
Examples: The design operated within a temperature range of 0-70 ...
I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.
Aotitude,core que on all subjects in ece
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
Worked on floorplanning, placement, and routing of digital designs
Utilized tools such as Cadence Innovus and Synopsys ICC
Collaborated with cross-functional teams to optimize design performance
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
posted on 1 Nov 2022
I applied via Referral and was interviewed before Nov 2021. There were 2 interview rounds.
I am interested in Freescale because of their innovative technology and strong reputation in the industry.
Freescale has a history of developing cutting-edge technology
Their reputation in the industry is strong and respected
I am excited about the opportunity to work with a company that values innovation and excellence
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Physical Design Engineer
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