Nvidia Interview Questions, Process, and Tips for Experienced

Q1. Os , CPP , bit manipulation
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Q1. Os , threads,cpp, python
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Q1. Tell me about yourself?
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Q1. Total 5 rounds were taken. 1 + 4 hours (back to back rounds). Questions were based on edt configuration and how changing it wil affect my design in terms of coverage and pattern count. How we can debug ser...read more
Ans. 
Edt configuration: Having more chains will cause less pattern compaction. IF you want to get data for a particular chain u have to send more patterns (Imagine at compressor you want to get data you have to mask all the other chains in the xor gate) hence more patterns needed. If we have single scan cell in a chain then less fault will be covered (only 2 patterns 1 and 0 can be sent). If high number of scan cells are th...read more
Answered by patteringshinchan
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Q2. Atspeed clock mechanisms. Questions on fault types. Circuit was drawn and I was asked to cover maximum faults for minimum number of patterns (3,5 i/p xor gate was drawn and how I can get s@ 1 s@0 faults fo...read more
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Q3. Can hold time/setup violation occur at stuckat capture.
Ans. 
Yes, hold time/setup violation can occur at stuckat capture.
• Stuck-at faults can cause hold time violations if the data is not held long enough for the capture register to sample it.

• Similarly, setup violations can occur if the data is not stable before the capture register samples it.

• These violations can be avoided by proper timing constraints and clocking strategies.

• For example, adding a delay to the clock signal can e...read more
Answered by AI
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Q4. Why can there be any coverage loss for 100% scan design.
Ans. 
Coverage loss can occur due to test pattern compression, test pattern generation, and test application issues.
• Test pattern compression can cause loss of coverage due to the reduction in the number of test patterns.

• Test pattern generation can result in coverage loss if the generated patterns do not cover all the faults.

• Test application issues such as timing violations or signal integrity problems can also lead to covera...read more
Answered by AI
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Q5. Questions on issues faced during ATPG, GLS coverage analysis.
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Q6. Difference between T3 and T5 violation.
Ans. 
T3 and T5 violations are related to timing constraints in digital circuits.
• T3 violation occurs when the data arrives too late at the destination register.

• T5 violation occurs when the data arrives too early at the destination register.

• T3 and T5 violations can cause setup and hold time violations.

• T3 and T5 violations can be fixed by adjusting the timing constraints or by adding delay elements.

• Examples of T3 and T5 violat...read more
Answered by AI
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Q1. Work related discussion session.
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Q1. Pick one question from 3 given questions and complete it in 7 days. I opted for creating traingle with opengl using shader.
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Data structures and algorithms
Problem were from leetcode and geek for geeks.

Q1. Data structures and algorithms
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Q1. Design and algorithms
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Coding round , questions from leetcode

Situation based questions and thought process

Q1. Managerial round 1, culture fit, behaviour
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Q2. Managerial round 2, innovative things done previously, how to face criticism, does experience matters in learning from subordinate
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