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Micron Technology
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I applied via Company Website and was interviewed in Apr 2024. There were 2 interview rounds.
What people are saying about Micron Technology
I applied via Referral and was interviewed in May 2022. There was 1 interview round.
Issues faced in post silicon for DFT Engineer
Coverage gaps can occur due to incomplete testing of certain functionalities
Wrapper cell issues can arise due to incorrect placement or sizing of the cells
Post silicon issues can also include timing violations, power issues, and signal integrity problems
Debugging post silicon issues can be challenging and time-consuming
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
I applied via LinkedIn and was interviewed in Feb 2024. There were 2 interview rounds.
ASML is a global leader in lithography technology, and I am excited about the opportunity to work on cutting-edge projects in the semiconductor industry.
ASML is a global leader in lithography technology
Excited about working on cutting-edge projects in the semiconductor industry
Opportunity for professional growth and development
I expect a challenging role where I can utilize my skills in embedded software development and contribute to innovative projects.
Expect to work on cutting-edge technologies in embedded systems
Desire to collaborate with a talented team to solve complex problems
Seek opportunities for professional growth and skill development
Expect a supportive work environment that values creativity and innovation
Yes, I have a valid visa.
Yes, I have a valid visa that allows me to work in this country.
My visa is valid until [expiration date].
I have all the necessary documentation to prove my visa status.
I heard about ASML through a job search website.
Job search website
Online job board
Referral from a friend who works at ASML
5-6 programming multiple choice questions on C++ and a problem to be solved with any language
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 10 Jul 2024
Yes, setup and hold uncertainty values are different in physical design engineering.
Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.
Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...
I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.
40 aptitude qns and some mcqs on basic programming
Given an array of integers, determine if there are two numbers that add up to a specific target.
Iterate through the array and store each element in a hash set.
For each element, check if the difference between the target and the element exists in the hash set.
If the difference exists, return true; otherwise, continue iterating.
Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
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