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I applied via Referral and was interviewed in May 2022. There was 1 interview round.
Issues faced in post silicon for DFT Engineer
Coverage gaps can occur due to incomplete testing of certain functionalities
Wrapper cell issues can arise due to incorrect placement or sizing of the cells
Post silicon issues can also include timing violations, power issues, and signal integrity problems
Debugging post silicon issues can be challenging and time-consuming
Top trending discussions
I applied via Campus Placement and was interviewed before Mar 2023. There were 2 interview rounds.
1st round consists of apt, digital , verilog , analog objective as well as descriptive questions in descriptive mostly related to fifo depth , counter and draw wave forms , analog questions were asked
I applied via Campus Placement and was interviewed before Apr 2023. There were 2 interview rounds.
Three coding questions and MCQ's
Types of memory allocations in C include static, dynamic, and automatic.
Static memory allocation: memory is allocated at compile time and remains constant throughout the program's execution. Example: int x = 5;
Dynamic memory allocation: memory is allocated at runtime using functions like malloc() or calloc(). Example: int *ptr = (int*)malloc(sizeof(int));
Automatic memory allocation: memory is allocated on the stack and...
Pointers in C are variables that store memory addresses. Types include null pointers, void pointers, function pointers, etc.
Null pointers: int *ptr = NULL;
Void pointers: void *ptr;
Function pointers: int (*ptr)(int, int);
I applied via Campus Placement and was interviewed in Mar 2024. There was 1 interview round.
I applied via Campus Placement and was interviewed in Jan 2022. There were 2 interview rounds.
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
I applied via Campus Placement and was interviewed in Dec 2023. There were 2 interview rounds.
I applied via Campus Placement and was interviewed in Aug 2021. There were 3 interview rounds.
I applied via Campus Placement and was interviewed before Jul 2022. There were 3 interview rounds.
Written test consist of digital electronics, coding section, verilog and aptitude questions
I applied via Company Website and was interviewed in Jun 2022. There were 3 interview rounds.
Basic Verilog coding and digital design questions
I have consistently maintained high grades throughout my academic career.
I have consistently achieved top grades in all my courses.
I have a GPA of 3.8 on a scale of 4.0.
I have received several academic awards and honors for my outstanding performance.
I have excelled in subjects like mathematics, computer science, and physics.
Some of the top questions asked at the Texas Instruments DFT Engineer interview -
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