Intel Interview Questions, Process, and Tips

Collaterals in PDK refer to additional files and documents that provide information and support for the Process Design Kit.

• Collateral files may include documentation on process technology, design rules, device models, and simulation parameters

• These collaterals help designers understand and utilize the PDK effectively

• Examples of collaterals in PDK are process design rules (PDR), technology files, and layout design guide

Soft connect errors in LVS can be resolved by adjusting the connectivity rules and verifying the layout.

• Review the connectivity rules to ensure they are correctly defined

• Check for any missing or incorrect connections in the layout

• Verify the layout against the design to identify and fix any discrepancies

• Use debugging tools to pinpoint the source of the soft connect errors

Parasitics of a device refer to unwanted electrical properties that affect its performance.

• Parasitics include resistance, capacitance, and inductance in a device.

• They can cause signal delays, power losses, and interference.

• Examples of parasitics are stray capacitance in a PCB trace or resistance in a wire.

• Minimizing parasitics is crucial for optimizing device performance.

A MOS capacitor can be built by creating a metal-oxide-semiconductor structure.

• Start by depositing a layer of oxide on a silicon substrate

• Then deposit a layer of metal on top of the oxide

• Finally, connect the metal layer to a terminal for the capacitor

HDL- Verilog coding, FSM, sequence detector.

verilog code for MUX, Sequence detector, half adder etc.