10+ DRS Infosystems Interview Questions and Answers

NAND and NOR structures are logic gates used in digital circuits. Their sizing varies based on the loads they need to drive.

• NAND and NOR gates are fundamental building blocks in digital circuit design.

• The size of NAND and NOR gates is determined by the number of inputs and the loads they need to drive.

• For NAND gates, the size of the transistors in the pull-up network is increased to handle larger loads.

• For NOR gates, the size of the transistors in the pull-down network is inc...read more

Yes, voltage scaling can help speed up a circuit by increasing the voltage to improve signal propagation.

• Increasing the voltage can reduce the resistance and capacitance effects, leading to faster signal propagation.

• Voltage scaling can also increase the switching speed of transistors, improving overall circuit performance.

• However, higher voltage levels may also increase power consumption and generate more heat, requiring careful design considerations.

• Example: In a digital cir...read more

Timing analysis changes for violating hold time and set up time constraints.

• For violating hold time constraint, the circuit needs to be redesigned to increase the delay of the data path.

• For violating set up time constraint, the circuit needs to be redesigned to decrease the delay of the data path.

• Hold time violations can be resolved by inserting additional flip-flops or increasing the clock-to-Q delay.

• Set up time violations can be resolved by reducing the propagation delay or...read more

Determine the heavy coin among 9 coins in the fewest number of tries.

• Divide the 9 coins into three groups of 3 coins each.

• Weigh any two groups against each other.

• If one group is heavier, weigh two coins from that group against each other.

• If they are equal, the remaining coin is the heavy one.

• If one coin is heavier, it is the heavy coin.

• If the initial weighing is balanced, the heavy coin is in the third group.

• Weigh two coins from the third group against each other to find the ...read more

Energy is consumed in transistors primarily in the form of heat.

• Energy is consumed in the form of heat due to resistive losses in the transistor.

• Switching between on and off states also consumes energy.

• Leakage current in transistors leads to energy consumption.

• Energy consumption can vary based on the transistor's size, material, and operating conditions.

Transistor level designs involve using transistors to create simple logic gates.

• Transistors can be used to create logic gates such as AND, OR, and NOT gates.

• In an AND gate, two transistors are connected in series.

• In an OR gate, two transistors are connected in parallel.

• In a NOT gate, a single transistor is used.

• Logic gates can be combined to create more complex circuits.

Gates can be represented using arithmetic operations like AND, OR, NOT, XOR, etc.

• AND gate can be represented using multiplication

• OR gate can be represented using addition

• NOT gate can be represented using subtraction

• XOR gate can be represented using modulo operation

• Arithmetic operations can be used to design complex logic circuits

Soft connect errors in LVS can be resolved by adjusting the connectivity rules and verifying the layout.

• Review the connectivity rules to ensure they are correctly defined

• Check for any missing or incorrect connections in the layout

• Verify the layout against the design to identify and fix any discrepancies

• Use debugging tools to pinpoint the source of the soft connect errors

Collaterals in PDK refer to additional files and documents that provide information and support for the Process Design Kit.

• Collateral files may include documentation on process technology, design rules, device models, and simulation parameters

• These collaterals help designers understand and utilize the PDK effectively

• Examples of collaterals in PDK are process design rules (PDR), technology files, and layout design guidelines

A MOS capacitor can be built by creating a metal-oxide-semiconductor structure.

• Start by depositing a layer of oxide on a silicon substrate

• Then deposit a layer of metal on top of the oxide

• Finally, connect the metal layer to a terminal for the capacitor

The design flow for chip development involves several stages, including specification, architecture, design, verification, and manufacturing.

• Specification: Define the requirements and functionality of the chip.

• Architecture: Determine the high-level structure and components of the chip.

• Design: Create the detailed circuitry and layout of the chip.

• Verification: Test and validate the chip design for functionality and performance.

• Manufacturing: Fabricate the chip using semiconduct...read more

A domino logic circuit is a type of digital circuit that uses a chain of inverters to propagate a signal.

• A domino logic circuit consists of a chain of inverters connected in series.

• The output of each inverter is connected to the input of the next inverter.

• The input signal is applied to the first inverter in the chain.

• The output of the last inverter in the chain is the output of the circuit.

• Domino logic circuits are faster than static CMOS circuits but consume more power.

Parasitics of a device refer to unwanted electrical properties that affect its performance.

• Parasitics include resistance, capacitance, and inductance in a device.

• They can cause signal delays, power losses, and interference.

• Examples of parasitics are stray capacitance in a PCB trace or resistance in a wire.

• Minimizing parasitics is crucial for optimizing device performance.