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Excel VLSI Technologies

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based on 11 Reviews

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Excel VLSI Technologies Design & Verification Engineer Interview Questions and Answers

Updated 9 Sep 2024

Excel VLSI Technologies Design & Verification Engineer Interview Experiences

1 interview found

Design & Verification Engineer Interview Questions & Answers

user image Anonymous

posted on 9 Sep 2024

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Asked about constraints
    • Add your answer
  • Q2. Simple d ff code
    • Add your answer
  • Q3. Difference between task and function
  • Ans. 

    Tasks are parallel processes that can run concurrently, while functions are sequential and return a value.

    • Tasks can run concurrently, while functions run sequentially

    • Tasks do not return a value, functions do

    • Tasks are defined using the 'task' keyword in Verilog, functions using the 'function' keyword

    • Answered by AI
    Add your answer
  • Q4. Difference between verilog tb and system verilog tb
  • Ans. 

    Verilog tb is used for Verilog testbenches while SystemVerilog tb is used for SystemVerilog testbenches.

    • Verilog tb uses Verilog language for testbenches while SystemVerilog tb uses SystemVerilog language.

    • SystemVerilog tb provides more advanced features like classes, randomization, and coverage.

    • SystemVerilog tb allows for easier integration of verification components and reuse of code.

    • Verilog tb may require more manual ...

    • Answered by AI
    Add your answer
  • Q5. How uvm methodology is useful
  • Ans. 

    UVM methodology is useful for creating reusable, scalable, and efficient verification environments in SystemVerilog.

    • UVM provides a standardized methodology for creating verification environments in SystemVerilog

    • It promotes reusability of verification components such as testbenches, sequences, and drivers

    • UVM helps in achieving better coverage closure and improves verification productivity

    • It enables easier debugging and ...

    • Answered by AI
    Add your answer

Skills evaluated in this interview

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Interview Tips & Stories
4d (edited)
timepasstiwari
·
A Digital Markter
Got Rejected In an Interview, Just Because I Didn’t Answer a Personal Question
So, I got invited for this interview, and they told me to be there at 9 AM. Of course, I get there early, like 8:30, because I don't want to be late. But then I end up waiting for 1.5 hours. Seriously, they didn't even acknowledge me until 10. Then this HR lady calls me in, and she's totally unprofessional. She's like, on her phone, making personal calls while I'm sitting right there. And then she starts asking me these really weird questions, like what my nickname is, and what my dad does for a living. It got really uncomfortable when she started pressing for details about where my dad works. I mean, what does that have to do with anything? So I politely told her I didn't want to answer, and she actually said, "Then we can't continue this interview." I was honestly shocked. But instead of arguing, I just stood up and said, “Alright then.” And walked out. I left feeling pissed. Not only did they waste an hour of my time, but the HR rep was also rude and unprofessional..
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Interview questions from similar companies

Design & Verification Engineer Interview Questions & Answers

Tessolve Semiconductor user image Anonymous

posted on 16 Aug 2023

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Naukri.com and was interviewed in Jul 2023. There were 2 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Technical 

(5 Questions)

  • Q1. SV, UVM, and interview questions related to AMBA protocol.
    • Add your answer
  • Q2. Logical questions based on constraint
    • Add your answer
  • Q3. Question based on SV oops
    • Add your answer
  • Q4. Question based on UVM tb
    • Add your answer
  • Q5. Question bases on assertions and coverage
    • Add your answer

Interview Preparation Tips

Interview preparation tips for other job seekers - SV, UVM, and some basic protocol.

Design & Verification Engineer Interview Questions & Answers

Einfochips user image Anonymous

posted on 1 Jun 2024

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed before Jun 2023. There were 2 interview rounds.

Round 1 - Technical 

(1 Question)

  • Q1. Digital logics , Verilog , System verilog , UVM , logical riddle
    • Add your answer
Round 2 - Technical 

(1 Question)

  • Q1. Projects related questions
    • Add your answer

Design & Verification Engineer Interview Questions & Answers

Tessolve Semiconductor user image mariyappan r

posted on 2 Dec 2024

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Aptitude+digital electronics+vhdl

Interview Preparation Tips

Interview preparation tips for other job seekers - Tough level questions

Design & Verification Engineer Interview Questions & Answers

Tessolve Semiconductor user image Anonymous

posted on 31 Dec 2024

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
No response

I was interviewed in Dec 2024.

Round 1 - Technical 

(2 Questions)

  • Q1. Sv hvm questions on constraiants and assertions
    • Add your answer
  • Q2. Questions on resume projects
    • Add your answer
Round 2 - Technical 

(2 Questions)

  • Q1. Questions on protocols
    • Add your answer
  • Q2. Sv uvm questions
    • Add your answer
Round 3 - HR 

(2 Questions)

  • Q1. Salary and pckge discussion
    • Add your answer
  • Q2. Details on client interview
    • Add your answer
Round 4 - Client Interview 

(2 Questions)

  • Q1. Projects and challenges
    • Add your answer
  • Q2. Sv uvm basics
    • Add your answer

Design & Verification Engineer Interview Questions & Answers

Tessolve Semiconductor user image Anonymous

posted on 11 Oct 2023

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed before Oct 2022. There were 2 interview rounds.

Round 1 - Aptitude Test 

A combination of Technical and Numerical aptitude. Questions on digital design, edc, vlsi.

Round 2 - One-on-one 

(3 Questions)

  • Q1. Questions on Digital Design
    • Add your answer
  • Q2. Questions on OOPS
    • Add your answer
  • Q3. Basic programming
    • Add your answer

Associate Software Engineer Interview Questions & Answers

Accenture user image Anonymous

posted on 10 Jul 2022

I applied via Campus Placement and was interviewed before Jul 2021. There were 4 interview rounds.

Round 1 - Aptitude Test 

Aptitude test on CS subjects like C programming, DBMS, CN, and OS.

Round 2 - Coding Test 

There were 2 input-output based questions of easy to moderate level

Round 3 - Group Discussion 

Every candidate was given an individual topic and was asked to speak on it

Round 4 - HR 

(1 Question)

  • Q1. Some typical HR questions
    • Add your answer

Interview Preparation Tips

Interview preparation tips for other job seekers - Be prepared with basic CS subjects you will be able to clear all rounds with ease.

Software Developer Interview Questions & Answers

TCS user image Ashish Kumar

posted on 15 Dec 2021

I applied via Company Website and was interviewed before Dec 2020. There were 4 interview rounds.

Interview Questionnaire 

1 Question

  • Q1. Questions on Java,SQL,some trending technologies(IOT,Big data),pattern questions, programming questions with different approaches.
    • Add your answer

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics of DSA, have knowledge about the databases, some common dml ,ddl statements, programming knowledge of a particular language like C,Java, python,etc...have good command on oops concepts... little bit of frameworks knowledge will also help

Associate Software Engineer Interview Questions & Answers

Accenture user image Anonymous

posted on 23 Jul 2022

I applied via Company Website and was interviewed before Jul 2021. There were 3 interview rounds.

Round 1 - Aptitude Test 

Aptitude, reasoning, English, cloud sections

Round 2 - Coding Test 

2 questions in which , one has to complete within an 50 minutes

Round 3 - Communication assessment 

(2 Questions)

  • Q1. Tell me about t Yourself
    • Add your answer
  • Q2. What are the previous experiences
    • Add your answer

Interview Preparation Tips

Topics to prepare for Accenture Associate Software Engineer interview:
  • Java
  • SQL
  • Agile Methodology
  • SDLC
Interview preparation tips for other job seekers - Be confident
Keep it just and short
Explain more about your experiences

System Engineer Interview Questions & Answers

TCS user image Anonymous

posted on 5 Jul 2022

I applied via Company Website and was interviewed before Jul 2021. There were 2 interview rounds.

Round 1 - Coding Test 

Attended the codevita competition in final year of college.

Round 2 - Technical 

(3 Questions)

  • Q1. About College Project
    • Add your answer
  • Q2. Some very basics of java
    • Add your answer
  • Q3. Experience of college project as a team
    • Add your answer

Interview Preparation Tips

Interview preparation tips for other job seekers - Codevita is a really good platform to help you join TCS as a final year graduate in college

Excel VLSI Technologies Interview FAQs

How many rounds are there in Excel VLSI Technologies Design & Verification Engineer interview?
Excel VLSI Technologies interview process usually has 1 rounds. The most common rounds in the Excel VLSI Technologies interview process are Technical.
What are the top questions asked in Excel VLSI Technologies Design & Verification Engineer interview?

Some of the top questions asked at the Excel VLSI Technologies Design & Verification Engineer interview -

  1. Difference between verilog tb and system verilog...read more
  2. How uvm methodology is use...read more
  3. Difference between task and funct...read more

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Excel VLSI Technologies Design & Verification Engineer Interview Process

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Excel VLSI Technologies Design & Verification Engineer Salary
based on 16 salaries
₹3 L/yr - ₹9.1 L/yr
19% less than the average Design & Verification Engineer Salary in India
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Excel VLSI Technologies Design & Verification Engineer Reviews and Ratings

based on 3 reviews

4.0/5

Rating in categories

3.9

Skill development

4.4

Work-life balance

4.0

Salary

3.6

Job security

4.4

Company culture

4.0

Promotions

4.3

Work satisfaction

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Excel VLSI Technologies Salaries in India
Design & Verification Engineer
16 salaries
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Physical Design Engineer
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Verification Engineer
4 salaries
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