Excel VLSI Technologies Interview Questions and Answers

Q1. Asked about constraints
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Q2. Simple d ff code
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Q3. Difference between task and function
Ans. 
Tasks are parallel processes that can run concurrently, while functions are sequential and return a value.
• Tasks can run concurrently, while functions run sequentially

• Tasks do not return a value, functions do

• Tasks are defined using the 'task' keyword in Verilog, functions using the 'function' keyword
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Q4. Difference between verilog tb and system verilog tb
Ans. 
Verilog tb is used for Verilog testbenches while SystemVerilog tb is used for SystemVerilog testbenches.
• Verilog tb uses Verilog language for testbenches while SystemVerilog tb uses SystemVerilog language.

• SystemVerilog tb provides more advanced features like classes, randomization, and coverage.

• SystemVerilog tb allows for easier integration of verification components and reuse of code.

• Verilog tb may require more manual ...read more
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Q5. How uvm methodology is useful
Ans. 
UVM methodology is useful for creating reusable, scalable, and efficient verification environments in SystemVerilog.
• UVM provides a standardized methodology for creating verification environments in SystemVerilog

• It promotes reusability of verification components such as testbenches, sequences, and drivers

• UVM helps in achieving better coverage closure and improves verification productivity

• It enables easier debugging and ...read more
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Questions regarding profit loss , percentage, time & work etc.

Q1. Digital electronics, verilog , semiconductor theory, Vlsi design, CMOS design
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Q1. Location related and basic HR questions
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