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I applied via Campus Placement and was interviewed in Jan 2024. There were 2 interview rounds.
There are 20 question related electronics
Latch up is a condition in integrated circuits where a parasitic thyristor is inadvertently triggered, causing a high current flow and potential damage to the circuit.
Latch up occurs when a parasitic thyristor in the IC is triggered, causing a short circuit between power and ground.
It can lead to a high current flow, potentially damaging the circuit.
Latch up can be triggered by high voltage spikes, electromagnetic inte...
Fabrication process in VLSI involves multiple steps to create integrated circuits on silicon wafers.
Photolithography: transferring circuit patterns onto silicon wafers
Etching: removing unwanted material using chemicals
Deposition: adding new material onto the wafer
Ion implantation: introducing dopants to alter conductivity
Annealing: heating the wafer to activate dopants and repair damage
Testing and packaging: final step
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I applied via Campus Placement and was interviewed in Jun 2021. There were 4 interview rounds.
posted on 31 Dec 2024
I was interviewed in Dec 2024.
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 15 Jan 2025
A FIFO checker is a verification component used to monitor and validate the behavior of a First-In-First-Out buffer in a design.
Implement a monitor that tracks the input and output operations of the FIFO buffer
Check that the data is read out in the same order it was written in
Verify that the FIFO buffer does not overflow or underflow
Use assertions to flag any violations of FIFO behavior
Example: Monitor the write and re...
posted on 24 Jul 2024
randc behavior generates random complex numbers with specified distribution
Use randc to generate random complex numbers
Specify distribution using arguments like mean, variance, etc.
Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.
40 aptitude qns and some mcqs on basic programming
Given an array of integers, determine if there are two numbers that add up to a specific target.
Iterate through the array and store each element in a hash set.
For each element, check if the difference between the target and the element exists in the hash set.
If the difference exists, return true; otherwise, continue iterating.
Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
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