Designo MediaWorks Interview Questions and Answers

Aptitude was quite easy with simple python questions

Asked basic questions on numpy and pandas

Q1. Python program questions
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Q2. OOPS based programming questions
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Q1. DSA - Linked List, Array and Strings
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Q1. Why should we hire you
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Q1. What is hyperparameter tuning?
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Hyperparameter tuning is the process of selecting the best set of hyperparameters for a machine learning model.
• Hyperparameters are parameters that are set before the learning process begins.

• Hyperparameter tuning involves adjusting hyperparameters to optimize the model's performance.

• Common techniques for hyperparameter tuning include grid search, random search, and Bayesian optimization.
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Q2. How do we train neural networks?
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Neural networks are trained using algorithms that adjust the weights and biases of the network based on the input data and desired output.
• Neural networks are trained using a process called backpropagation, where the error between the predicted output and the actual output is used to adjust the weights and biases of the network.

• Training data is fed into the neural network, and the network's output is compared to the des...read more
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Q3. What is overfitting?
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Overfitting occurs when a machine learning model learns the training data too well, including noise and outliers, leading to poor generalization on new data.
• Overfitting happens when a model is too complex and captures noise in the training data.

• It can be identified when a model performs well on training data but poorly on unseen data.

• Techniques to prevent overfitting include cross-validation, regularization, and early ...read more
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Q1. Easy to crack be confident
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Q2. Geniune questions
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Q3. Salary expectation
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Q4. Immediate joining
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Q1. Details of UVM and System Verilog blocking and non blocking assignment
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UVM is a methodology for verifying complex designs using SystemVerilog. Blocking assignments execute sequentially, while non-blocking assignments execute concurrently.
• UVM (Universal Verification Methodology) is a standardized methodology for verifying complex designs in SystemVerilog.

• Blocking assignments in SystemVerilog execute sequentially, meaning the next statement waits for the current statement to finish.

• Non-bloc...read more
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Q1. Where do you see yourself in 5 years and strength and weakness
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Q1. Ofdm, equalization, estimation
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Q1. Ofdm, equalization, estimation
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