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I applied via Job Portal and was interviewed before Apr 2022. There were 2 interview rounds.
Implement 2 stage XOR gate using 2 stage NAND gate.
Construct 2 stage NAND gate using 4 NAND gates.
Connect the output of first stage NAND gate to the input of second stage NAND gate.
Connect the output of second stage NAND gate to the input of first stage NAND gate.
The output of second stage NAND gate is the output of the XOR gate.
Implementing dff using 2:1 mux
Connect the input to the select line of the mux
Connect the output of the mux to one of the inputs of the mux
Connect the output of the dff to the other input of the mux
Connect the output of the mux to the input of the dff
I applied via LinkedIn and was interviewed before Jun 2022. There were 4 interview rounds.
There are mcqs questions will be in exam on Aptitude, C language, Digital Electronics. Those are like GATE Level questions.
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