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Beceem Communications Design Engineer Interview Questions and Answers

Updated 19 Sep 2015

Beceem Communications Design Engineer Interview Experiences

1 interview found

Interview Questionnaire 

6 Questions

  • Q1. Thesis-based questions
  • Q2. Project-based questions
  • Q3. What would you do to remove Setup violation, hold violation?
  • Ans. 

    To remove Setup violation, hold violation, I would optimize the timing constraints and perform timing analysis.

    • Optimize timing constraints to ensure that setup and hold times are met

    • Perform timing analysis to identify and resolve any timing violations

    • Use delay constraints to ensure that signals arrive at the correct time

    • Use clock skew optimization to minimize clock skew and improve timing

    • Use clock gating to reduce powe...

  • Answered by AI
  • Q4. Do you know about verilog?
  • Ans. 

    Yes, Verilog is a hardware description language used to design digital circuits.

    • Verilog is used to design digital circuits at various levels of abstraction.

    • It is commonly used in the design of integrated circuits and field-programmable gate arrays (FPGAs).

    • Verilog is used to describe the behavior of a circuit and its components.

    • It is also used for simulation and verification of digital circuits.

    • Verilog has a syntax simi

  • Answered by AI
  • Q5. Questions based on timing analysis
  • Q6. Are you interested in persuing PhD. ?
  • Ans. 

    Yes, I am interested in pursuing a PhD.

    • I have always been passionate about research and innovation.

    • I believe a PhD will provide me with the opportunity to delve deeper into my field of interest.

    • I am also interested in teaching and a PhD will open up more opportunities in academia.

    • I have already started exploring potential research topics and universities.

    • I am aware of the challenges and commitment required for a PhD an

  • Answered by AI

Interview Preparation Tips

Round: Test
Experience: There were some basic questions on probability theory, digital communication (mainly wireless communication, like problem on GSM, CDMA, and OFDM). Some questions were from DSP (like DFT etc.). Basics of information theory (EE 624) should be clear; there were some questions on calculating capacity of a Gaussian channel, differential entropy etc. A single problem from C programming was there and it was very simple.
Two sections : 1) VLSI 2) Communications

For VLSI stream we had to solve only the first section.

Type of questions and details :
Questions were a mix of digital and analog.
Most of the questions were on digital logic design.
1) Given a current mirror circuit we had to identify and calculate what is the current through one MOS Transistor.
2) Question on timing analysis-setup time, hold time ----this very important---you have to be very clear in this concept. Frequently asked.
3) Question on Op Amp. It was an integrator …had to calculate output voltage.
4) Many questions were on logic design.
5) Questions on devices like if doping increased, how would the other parameters vary..?
Duration: 60 minutes
Total Questions: 30

Round: Technical Interview
Experience: View 1: He asked me most of the questions on my thesis and my previous projects and term papers (related to wireless communication). I was also asked about viterbi decoders, OFDM and MIMO (my thesis was on MIMO).
View 2: Questions were mostly on timing analysis.

General Tips: One should try to keep himself focused during the whole time of written test and interview. Basics of probability theory and communication theory should be very clear.
Skill Tips: Be well prepared with both digital and analog. You must know Verilog.
Skills: Probability, Coding, Information Theory, Wireless communication
College Name: IIT- Kanpur

Skills evaluated in this interview

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
4-6 weeks
Result
Selected Selected

I applied via Walk-in and was interviewed in Jun 2024. There was 1 interview round.

Round 1 - HR 

(2 Questions)

  • Q1. Education background
  • Q2. Working background

Interview Preparation Tips

Interview preparation tips for other job seekers - Very simple interview but they took extra time to give you offer letter
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
4-6 weeks
Result
Selected Selected

I applied via Walk-in and was interviewed in Jun 2024. There was 1 interview round.

Round 1 - HR 

(2 Questions)

  • Q1. Education background
  • Q2. Working background

Interview Preparation Tips

Interview preparation tips for other job seekers - Very simple interview but they took extra time to give you offer letter

Beceem Communications Interview FAQs

What are the top questions asked in Beceem Communications Design Engineer interview?

Some of the top questions asked at the Beceem Communications Design Engineer interview -

  1. What would you do to remove Setup violation, hold violati...read more
  2. Do you know about veril...read more
  3. Questions based on timing analy...read more

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