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SQL joins are used to combine rows from two or more tables based on a related column between them.
Types of joins include INNER JOIN, LEFT JOIN, RIGHT JOIN, and FULL JOIN.
INNER JOIN returns rows when there is at least one match in both tables.
LEFT JOIN returns all rows from the left table and the matched rows from the right table.
RIGHT JOIN returns all rows from the right table and the matched rows from the left table.
F...
Commands of docker, git
I applied via campus placement at Vellore Institute of Technology (VIT) and was interviewed in Apr 2022. There were 2 interview rounds.
Static analysis is done without executing the code while dynamic analysis is done during code execution.
Static analysis is done by analyzing the code without executing it
Dynamic analysis is done by analyzing the code during its execution
Static analysis is usually done before the code is compiled or executed
Dynamic analysis is usually done after the code is compiled or executed
Static analysis can detect potential issues...
Altair Engineering interview questions for designations
Top trending discussions
I applied via Campus Placement and was interviewed in Feb 2024. There were 2 interview rounds.
Digital electronics, circuits , verilog , asic design flow
ASIC design flow process involves steps like specification, design, verification, synthesis, and testing.
Specification: Define requirements and constraints for the ASIC design.
Design: Create a high-level design based on the specifications.
Verification: Verify the design using simulations and tests.
Synthesis: Convert the design into a netlist of gates and connections.
Testing: Test the fabricated ASIC to ensure functiona...
Power reduction techniques in CMOS involve various methods to minimize power consumption in CMOS circuits.
Use of power gating to selectively turn off power to unused circuit blocks
Implementing clock gating to disable clock signals to unused circuitry
Utilizing voltage scaling to reduce power consumption at lower voltages
Applying dynamic voltage and frequency scaling to adjust voltage and frequency based on workload
Using...
I applied via Referral and was interviewed in Dec 2023. There was 1 interview round.
I applied via campus placement at G Pulla Reddy Engineering College, Kurnool and was interviewed in Oct 2023. There were 2 interview rounds.
It was conducted through hackerrank platform which contains 5 programming questions
There were 3 sections
To switch variable values, use a temporary variable to hold one value while swapping the other.
Create a temporary variable to hold the value of one variable
Assign the value of the second variable to the first variable
Assign the value of the temporary variable to the second variable
Create a small code
I applied via Campus Placement and was interviewed in Feb 2024. There were 2 interview rounds.
Digital electronics, circuits , verilog , asic design flow
ASIC design flow process involves steps like specification, design, verification, synthesis, and testing.
Specification: Define requirements and constraints for the ASIC design.
Design: Create a high-level design based on the specifications.
Verification: Verify the design using simulations and tests.
Synthesis: Convert the design into a netlist of gates and connections.
Testing: Test the fabricated ASIC to ensure functiona...
Power reduction techniques in CMOS involve various methods to minimize power consumption in CMOS circuits.
Use of power gating to selectively turn off power to unused circuit blocks
Implementing clock gating to disable clock signals to unused circuitry
Utilizing voltage scaling to reduce power consumption at lower voltages
Applying dynamic voltage and frequency scaling to adjust voltage and frequency based on workload
Using...
I applied via Referral and was interviewed in Dec 2023. There was 1 interview round.
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