DFT Engineer - ATPG/MBIST (3-5 yrs)

About the Job :

We are looking for a talented and detail-oriented DFT Engineer with a minimum of 3 years of hands-on experience in Design for Testability. The ideal candidate will possess a strong technical background in DFT methodologies, including ATPG, MBIST, Scan Insertion, and Silicon Debugging, along with excellent scripting and debugging skills.

Key Responsibilities :

DFT Implementation :

- Develop and implement DFT architectures and methodologies for complex SoCs and ASICs.

- Perform Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), and Scan Insertion processes.

- Generate, simulate, and verify ATPG, MBIST, and LBIST (Logic Built-In Self-Test) patterns to ensure robust test coverage and design integrity.

Pattern Porting & Verification :

- Understand the requirements for pattern porting from block level to top level and execute them efficiently.

- Collaborate with design and verification teams to ensure seamless integration of DFT features across various design hierarchies.

DFT Architecture & ICL Network :

- Develop a thorough understanding of DFT architecture, including scan chains, boundary scan (JTAG), and BIST techniques.

- Apply knowledge of ICL (Interconnect Logic) network design and its impact on testability and design performance.

Timing & STA Constraints :

- Work with timing analysis teams to define and validate Static Timing Analysis (STA) constraints related to DFT modes.

- Ensure timing closure and resolve any STA violations in test modes.

Silicon Debugging & Validation :

- Participate in post-silicon bring-up and debug activities, analyzing test results, identifying failures, and providing solutions.

- Leverage silicon debug tools and methodologies to improve test coverage and reduce test time.

Required Skills and Experience :

- 3+ years of hands-on experience in DFT with a strong emphasis on debugging and scripting.

- Proficient in ATPG, MBIST, Scan Insertion, and pattern simulation/verification techniques.

- Strong understanding of DFT architecture, ICL network, and STA constraints.

- Experience with Silicon Debug and bring-up processes (preferred).

- Proficient in scripting languages such as TCL, Perl, Python, or similar, to automate design and verification tasks.

- Familiarity with industry-standard EDA tools for DFT (e.g., Synopsys, Mentor Graphics, Cadence).

- Excellent problem-solving skills and the ability to work effectively in a collaborative team environment.