Tessolve - Senior DFT Engineer - SoC (4-7 yrs)

Requirements :

- DFT implementation using DFT flow for Tessent

- DFT test pattern generation & verification

- Participate to SoC test Specification

- MBIST test pattern generation & verification

- Support test engineer for production test debug and improvement

- Collaborate with cross functional teams in Design flow improvement

- Overcome design challenges, support achievement of quality goals

Requirements/Qualifications :

Qualifications/Experience :

- Excellent understanding of Design For Test (Scan, ATPG, Memory Bist, Boundary Scan)

- Working experience with Tessent Siemens flow for SCAN , Memory BIST & Boundary Scan

- Understanding of JTAG/IJTAG/1500/1687/1149.1 networks

- Good knowledge in ICL and PDL

- Working experience in Test pattern development, simulation, and debug

- Good knowledge in hardware description languages (e.g. Verilog, VHDL, Verilog-AMS, SystemVerilog)

- Previous experience and proficiency in any one of commonly used scripting languages (Perl, TCL, ..)

- Knowledge of revision control mechanisms

- Superior Written and Verbal Communication skills

- Experience working with cross functional global teams

Preferred Skills :

- Experience with Equivalence Checking tool (Cadence LEC), Synthesis and Static timing analysis, CDC experience.

- Experience with Synospsys tools : DC, FC, TMAX will be also appreciated.

- Experience with QUESTA, Xcelium

- Experience with data management systems (e.g., Subversion, DesignSync)

- Knowledge of Functional Safety / ISO26262 standards