ASIC Digital Design, Sr Staff Engineer

• The selected candidate will be a key member of the Synopsys DesignWare ARC Processor hardware verification team.
• Responsibility includes ownership of complete verification process including creation of test plans, development of testbenches, creation of tests - both directed and random, functional coverage modelling and analysis, code coverage analysis, debugging and resolving mismatches between design and C-model, integration of third party and internal verification IP, regression management, review and improvement of verification test suites.
• Candidate should be able to lead verification team and provide guidance and mentorship. Candidate should be able to represent team in various forums with global audience.

Job Requirements :

• bachelors degree in engineering is required as a minimum from a reputed college
• Minimum eight years of experience in digital front end functional verification
• Microprocessor architecture knowledge
• HDL and Verification languages: SystemVerilog, Verilog
• Verification methodologies: UVM/OVM
• Programming skills: C, assembly, Perl, makefile generation
• Tools: RTL Simulators, eg VCS.
• Experience in technical leadership of a verification team
• Experience in working with global teams

Written and Verbal communication skills:

• Creation, modification and review of test documentation: testplans, procedures, test scenarios, test reports
• Ability to represent verification team in global platforms

Analytical skills:

• Analysis of verification requirements to close out on product release
• Ability to analyze test results and provide reports
• Provide guidance to team based on result analysis

• Self-motivated team player able to thrive in a fast-paced engineering environment
• Inspire team for technical excellence