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ASIC Digital Design, Staff Engineer
3-5 years
Hyderabad / Secunderabad
1 vacancy
ASIC Digital Design, Staff Engineer
Synopsys
posted 4mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- 3 to 5 year experience in Digital verification using UVM/VMM methodology.
- Good Knowledge on Verilog , system Verilog, VMM/UVM methodologies. Ability to create and debug mixed signal testbenches as per the design requirements.
- Implementing mixed signal checkers and measurements for the verification of mixed signal design
- Good knowledge on scripting languages like perl, python.
- Right attitude for exploring the design verification environment and come up with solutions for improving the flow/methodologies
- Selected candidate will be a part of highly motivated and challenging high speed PHY design team working on latest technologies
Employment Type: Full Time, Permanent
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(based on 53 Synopsys interviews) What people at Synopsys are saying
Rating based on 4 Staff Engineer
reviews
Anonymous · Software Development
in Noida
Work wise company is good.
Poor work culture. No Work Life balance. Managers expects employee to work on weekends. Beware if your manager is from Attrenta(Synopsys aquired Attrenta), they are really toxic to work with.
Read 4 reviewsStaff Engineer salary at Synopsys
What Synopsys employees are saying about work life
Synopsys Benefits
EMPLOYEE LED WELFARE FUND TUITION REIMBURSEMENT PROGRAM EMPLOYEE ASSISTANCE PROGRAM (EAP) LOAN PROGRAM 
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Synopsys Hyderabad / Secunderabad Office Location
500032
