DFT Engineer - MBIST/ATPG (1-10 yrs)

Position Vacant : "Design for testability" [DFT]

Location : Bangalore

Work Mode : WFO

No of days working : 5days

Experience : 1-10+ years

Availability : Immediate to 30 days joiners

Role Description:

This is a full-time opportunity for "Design for testability [DFT]" with SEMI LEAF located in Bengaluru. The candidate will be responsible for day-to-day tasks associated with present role with our clients.

Job Description :

1. Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off.

2. Working for a comprehensive DFT plan, drive the implementation and work with DFT cross functional teams.

3. ATPG generation, including Netlist debug for issues and having resolved same with Backend team

4. MBIST experience.

5. Supporting PostSi team for pattern generation issues

6. Proven expertise in implementing and validating DFX methodologies in ASIC/SoC designs.

7. Work closely with RTL design, physical design, and verification teams to integrate DFX methodologies throughout the design flow.

8. Perform simulations to validate DFX features, including test coverage analysis and yield simulation.

9. Proficiency in DFT tools such as Synopsys DFT Compiler, Cadence Modus, or Mentor Tessent.

10. Strong understanding of scan chains, MBIST, LBIST, and ATPG.

11. Familiarity with DFM guidelines and process technologies from leading foundries (e.g., TSMC, Intel).

12. Provide feedback and recommendations to improve design quality and manufacturability.

13. Support post-silicon validation and bring-up activities.

14. Hands-on experience with simulation and verification tools like VCS, QuestaSim, or Xcelium.

15.Proficiency in scripting languages (e.g., Python, Perl, TCL)

16. Experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.