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Cadence Design Systems - DFT Engineer - RTL (8-15 yrs)

8-15 years

Cadence Design Systems - DFT Engineer - RTL (8-15 yrs)

Cadence Design Systems

posted 1mon ago

Job Description

Job Summary :

Join a growing and dynamic team and help lead the Design for Test activities for next generation of SoCs in advanced technology nodes.

As part of the HSV SoC design team, you will be working to define and implement the Design-for-Test architecture and features for SoCs for Palladium- Emulation platforms in advanced technology nodes.

Key Responsibilities :

- Define the DFT Architecture for the next generation SoCs.

- Implementation & verification including Scan, PMBIST, JTAG and other DFT's related logic.

- Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc.

- Working closely with cross functional teams to develop and verify DFT's structures and constraints.

- Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality.

- Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.

- Work closely with EDA RnD teams to propose and implement new features.

Requirements :

- BTech /BE/ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT).

- Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.

- Working knowledge of RTL coding in Verilog, Synthesis & STA.

- Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred.

- Hands on experience with either Tessent/Modus ATPG tool.

- Proven success in development of complex custom ASIC products in advanced process nodes.

- Hands-on experienced and successful taped out several ASICs.

- Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.

- Excellent written and verbal communication skills.


Functional Areas: Other

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Prepare for DFT Engineer roles with real interview advice

Top Cadence Design Systems DFT Engineer Interview Questions

Q1. Find All Pairs with Given Sum Given an integer array arr and an integer Sum , count and return the total number of pairs in the array whose ... read more
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What people at Cadence Design Systems are saying

DFT Engineer salary at Cadence Design Systems

reported by 1 employee
₹15.3 L/yr - ₹19.6 L/yr
79% more than the average DFT Engineer Salary in India
View more details

What Cadence Design Systems employees are saying about work life

based on 272 employees
87%
90%
71%
90%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

Cadence Design Systems Benefits

Cafeteria
Work From Home
Health Insurance
Team Outings
Gymnasium
Soft Skill Training +6 more
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