RTL Engineer - System Verilog (5-12 yrs)

Role : RTL Engineers

Location : Bangalore

Experience : 5 - 10+ years

Availability : Immediate to 30 days joiners

Qualification : BE/BTech/ME/MTech

Role Description :

This is a full-time on-site opportunity for "RTL Engineers" [RTL] Engineer" with SEMI LEAF located in Bengaluru. The candidate will be responsible for day-to-day tasks associated with present role with our clients.

Job Description :

- Expertise in SoC subsystem/IP design

- Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

- In depth knowledge on RTL quality checks (Lint, CDC)

- Knowledge of synthesis and low power is a plus

- Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

- Good understanding of timing concepts

- Knowledge of one or more of the interface protocols[PCIE, DDR, Ethernet, I2C, UART, SPI]

- Expertise in setting up and using tools like [Spyglass Lint/CDC, Synopsys DC, Verdi/Xellium]

- Understanding of scripting languages like Make flow, Perl ,shell, python etc

- Understanding of processor architecture and/or ARM debug architecture is a plus

- Able to help and debug issues for multiple subsystems

- Able to create/review design documents for multiple subsystems

- Able to support physical design, verification, DFT and SW teams on design queries and reviews