Design Verification Engineer - UVM (8-15 yrs)

Job requirements : Technical Skills

- 8+ years of experience in UVM verification and UVM environment development (must have).

- Proficient in test plan definition and test case development in C/Assembly/System Verilog.

- Expertise in verifying design at RTL level and gate-level simulation.

- Good understanding of coverage analysis, performance verification, and use-case verification.

- Must have worked on AMBA AXI, AHB, and APB protocols.

- Should have worked on verifying interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.

- Experience in functional test vector development and post-silicon bring-up/debug.

- Fluency with scripting languages (e.g., Perl, Python, Shell).

- Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA.

- Education : B.Tech/BE/ME/M.Tech

Job requirements : Soft Skills

Communication :

- Able to abstract technical details.

- Open to communicate with people on and off site. Open-minded.

- Excellent communication skills, enjoys working in an international team across locations

- Very good level of spoken and written English ( at least B2 level).

- Strong presentation and listening skills are required Team player

- Committed to the team and task

- Helping team members, sharing knowledge Self-driven and highly motivated

- Self-motivated and self-dependent worker. Embracing the task.

- Highlight potential issues

- Regular reporting.

- Clean and organized working style.

- Able to go the extra mile Solution oriented attitude, pragmatic. Good problem solving skills

- Following and improving processes

- Able to follow corporate reporting standards Organized, trusted, committed to a long term employment

- Quality awareness